參數(shù)資料
型號: KM48S2020C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1M x 8Bit x 2 Banks Synchronous DRAM(1M x 8位 x 2組同步動態(tài)RAM)
中文描述: 1M × 8位× 2銀行同步DRAM(1米× 8位× 2組同步動態(tài)RAM)的
文件頁數(shù): 2/44頁
文件大?。?/td> 605K
代理商: KM48S2020C
KM48S2020C
REV. 5 Feb. '98
CMOS SDRAM
The KM48S2020C is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 1,048,576 words by 8 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS latency ( 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
GENERAL DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1M x 8Bit x 2 Banks Synchronous DRAM
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
1M x 8
1M x 8
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
Timing Register
ORDERING INFORMATION
Part No.
Max Freq.
125MHz
100MHz
100MHz
100MHz
Interface Package
KM48S2020CT-G/F8
KM48S2020CT-G/FH
KM48S2020CT-G/FL
KM48S2020CT-G/F10
LVTTL
44
TSOP(II)
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