參數(shù)資料
型號(hào): KM48S2020C
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 1M x 8Bit x 2 Banks Synchronous DRAM(1M x 8位 x 2組同步動(dòng)態(tài)RAM)
中文描述: 1M × 8位× 2銀行同步DRAM(1米× 8位× 2組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 1/44頁(yè)
文件大?。?/td> 605K
代理商: KM48S2020C
KM48S2020C
REV. 5 Feb. '98
CMOS SDRAM
Revision History
Revision .4(November 1997)
- t
RDL
has changed 10ns to 12ns.
- Binning -10 does not meet PC100 characteristics .
So AC parameter/Characteristics have changed to 16M 3rd values.
Revision .5 (Feb. 1998)
- Input leakage Currents (Inputs / DQ) are changed.
I
IL
(Inputs) :
±
5uA to
±
1uA, I
IL
(DQ) :
±
5uA to
±
1.5uA.
- The measuring condition of t
R
/t
F
is clearly defined each as
0pF +50
to V
SS
/V
DD
, 50pF +50
to V
SS
/V
DD
- Cin to be measured at V
DD
= 3.3V, T
A
= 23
°
C, f = 1MHz, V
REF
=1.4V
±
200 mV.
AC Operating Condition is changed as defined ;
- V
IH
(max) = 5.6V AC. The overshoot voltage duration is
3ns.
V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
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