參數(shù)資料
型號： KM48C514D
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： High Speed 512K x 8Bit CMOS Dynamic RAM with Extended Data Out(高速512K x 8位 CMOS 動態(tài)RAM(帶擴展數(shù)據(jù)輸出))
中文描述： 高速的擴展數(shù)據(jù)輸出（高速為512k × 8位的CMOS動態(tài)隨機存儲器（帶擴展數(shù)據(jù)輸出）的CMOS為512k × 8位動態(tài)隨機存儲器）
文件頁數(shù)： 7/21頁
文件大?。?/td> 393K
代理商： KM48C514D
KM48C514D
CMOS DRAM
High Speed
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Transition times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL load and 30pF. Dout reference level : Voh/Vol=2.0V/0.8V
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min),
t
AWD
≥
t
AWD
(min) and
t
CPWD
≥
t
CPWD
(min) then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above con-
ditions is satisfied, the condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
This parameters is referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and
read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
t
ASC
≥
6ns, Assume t
T
= 2.0ns
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
If
t
RASS
≥
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 1024(1K) cycle of burst refresh must be executed within
16ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immedi-
ately before and after self refresh in order to meet refresh specification.
7.
6.
5.
10.
9.
8.
12.
11.
3.
2.
1.
4.
13.
NOTES
14.
15.
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