參數資料
型號: KM44S16030B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 4Bit x 4 Banks Synchronous DRAM(4M x 4位 x 4組同步動態(tài)RAM)
中文描述: 4米× 4位× 4銀行同步DRAM(4米× 4位× 4組同步動態(tài)RAM)的
文件頁數: 38/43頁
文件大?。?/td> 625K
代理商: KM44S16030B
TIMING DIAGRAM - III
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ELECTRONICS
REV. 2 Mar. '98
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page
HIGH
Row Active
(A-Bank)
: Don't care
*Note :
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is same as the case of
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
3. Burst stop is valid at every burst length.
RAS interrupt.
Precharge
(A-Bank)
Burst Stop
Read
(A-Bank)
Read
(A-Bank)
1
2
1
2
BA
0
BA
1
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
QAa0 QAa1 QAa2 QAa3 QAa4
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
QAb0 QAb1 QAb2 QAb3
QAb4 QAb5
RAa
CAa
CAb
RAa
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