參數(shù)資料
型號(hào): KM44S16030B
廠(chǎng)商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 4Bit x 4 Banks Synchronous DRAM(4M x 4位 x 4組同步動(dòng)態(tài)RAM)
中文描述: 4米× 4位× 4銀行同步DRAM(4米× 4位× 4組同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 32/43頁(yè)
文件大?。?/td> 625K
代理商: KM44S16030B
TIMING DIAGRAM - III
CMOS SDRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ELECTRONICS
REV. 2 Mar. '98
Page Read Cycle at Different Bank @Burst Length=4
HIGH
Row Active
(A-Bank)
Read
(A-Bank)
Read
(C-Bank)
Precharge
(B-Bank)
Read
(D-Bank)
: Don't care
*Note :
1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Row Active
(B-Bank)
*Note 2
*Note 1
Row Acive
(C-Bank)
Read
(B-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Precharge
(C-Bank)
Precharge
(D-Bank)
BA
0
BA
1
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
QAa0 QAa1
QAa2
QBb0
QBb1 QBb2 QCc0 QCc1 QCc2
QDd0 QDd1 QDd2
QAa0 QAa1
QAa2 QBb0
QBb1 QBb2 QCc0
QCc1
QCc2 QDd0 QDd1 QDd2
RAa
RBb
RCc
RDd
RAa
RBb
CAa
RCc
CBb
RDd
CCc
CDd
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