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參數(shù)資料
| 型號(hào)： | KM44C1003D |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode(1M x 4位CMOS四 CAS 動(dòng)態(tài)RAM(帶快速頁模式)) |
| 中文描述： | 100萬x 4位的CMOS DRAM與四中科院快速頁面模式（1米× 4位的CMOS四中科院動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶快速頁模式）） |
| 文件頁數(shù)： | 1/21頁 |
| 文件大?。?/td> | 388K |
| 代理商： | KM44C1003D |
KM44C1003D
CMOS DRAM
This is a family of 1,048,576 x 4bit Fast Page Mode Quad CAS CMOS DRAMs. Fast Page Mode offers high speed random access of
memory cells within the same row. Access time (-5, -6 or -7), power consumption(Normal), and package type (SOJ or TSOP-II) are
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. All
inputs and outputs are fully TTL compatible and four seperate CAS pins provide for seperate I/O operation allowing this device to oper-
ate in parity mode. This 1Mx4 Fast Page Mode DRAM family is fabricated using Samsung
′
s advanced CMOS process to realize high
band-width, low power consumption and high reliability.
Part Identification
- KM44C1003D(5V)
Fast Page Mode operation
Four seperate CAS pins provide for seperate I/O
operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Fast parallel test mode capability
TTL compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in 26(24)-pin SOJ 300mil and TSOP(II)
300mil packages
Single +5V
±
10% power supply
Control
Clocks
RAS
CAS0~3
W
Vcc
Vss
DQ0
to
DQ3
Memory Array
1,048,576 x 4
Cells
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
1M x 4bit CMOS Quad CAS DRAM with Fast Page Mode
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles
Part
NO.
Refresh
cycle
Refresh Period
Normal
16ms
KM44C1003D
1K
Performance Range
Speed
-5
-6
-7
t
RAC
50ns
60ns
70ns
t
CAC
15ns
15ns
20ns
t
RC
90ns
110ns
130ns
t
PC
35ns
40ns
45ns
Active Power Dissipation
Speed
-5
-6
-7
Active power dissipation
470
415
360
Unit : mW
S
Data out
Buffer
Data in
Buffer
OE
A0~A9
Row Address Buffer
Col. Address Buffer
Column Decoder
Row Decoder
Refresh Timer
Refresh Control
Refresh Counter
VBB Generator
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