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參數(shù)資料
| 型號(hào)： | KM432V515 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 32Bit CMOS Quad CAS DRAM with EDO(512K x 32位CMOS四 CAS 動(dòng)態(tài)RAM(帶EDO模式)) |
| 中文描述： | 為512k × 32Bit的中科院的CMOS四路DRAM與江戶(hù)（512k × 32的位的CMOS四中科院動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶EDO公司模式）） |
| 文件頁(yè)數(shù)： | 5/21頁(yè) |
| 文件大?。?/td> | 400K |
| 代理商： | KM432V515 |
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CMOS DRAM
KM432V515
Preliminary
CAPACITANCE
(T
A
=25
°
C
, V
CC
=3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A9]
C
IN1
-
5
pF
Input capacitance [RAS, CASx, W, OE]
C
IN2
-
7
pF
Output capacitance [DQ0 - DQ31]
C
DQ
-
7
pF
Test condition (3.3V device) : V
CC
=3.3V
±
0.3V, Vih/Vil=2.2/0.8V, Voh/Vol=2.0/0.8V
Parameter
Symbol
Min
Max
Units
Notes
Random read or write cycle time
t
RC
t
RWC
104
ns
Read-modify-write cycle time
140
ns
Access time from RAS
t
RAC
t
CAC
60
ns
3,4,10
Access time from CAS
17
ns
3,4,5,18
Access time from column address
t
AA
t
CLZ
30
ns
3,10
CAS to output in Low-Z
3
ns
3,18
Output buffer turn-off delay from CAS
t
CEZ
t
OLZ
3
15
ns
6,11,18
OE to output in Low-Z
3
ns
3
Transition time (rise and fall)
t
T
t
RP
2
50
ns
2
RAS precharge time
40
ns
RAS pulse width
t
RAS
t
RSH
60
10K
ns
RAS hold time
17
ns
14
CAS hold time
t
CSH
t
CAS
48
ns
17
CAS pulse width
12
10K
ns
23
RAS to CAS delay time
t
RCD
t
RAD
20
43
ns
4,16
RAS to column address delay time
15
30
ns
10
CAS to RAS precharge time
t
CRP
t
ASR
5
ns
15
Row address set-up time
0
ns
Row address hold time
t
RAH
t
ASC
10
ns
Column address set-up time
0
ns
16
Column address hold time
t
CAH
t
RAL
10
ns
16
Column address to RAS lead time
30
ns
Read command set-up time
t
RCS
t
RCH
0
ns
Read command hold time referenced to CAS
0
ns
8,15
Read command hold time referenced to RAS
t
RRH
t
WCH
0
ns
8
Write command hold time
10
ns
14
Write command pulse width
t
WP
t
RWL
10
ns
Write command to RAS lead time
15
ns
Write command to CAS lead time
t
CWL
t
DS
10
ns
17
Data set-up time
0
ns
9
Data hold time
t
DH
10
ns
9
AC CHARACTERISTICS
(0
°
C
≤
T
A
≤
70
°
C
, See note 1,2)
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