參數(shù)資料
型號： KM432D5131
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 128K x 32Bit x 4 Banks Double Data Rate Synchronous Graphic RAM with Bi-directional Data Strobe(128K x 32位 x 4 組雙速率同步圖形RAM帶雙向數(shù)據(jù)選通)
中文描述： 128K的x 32Bit的× 4銀行雙數(shù)據(jù)速率同步圖形RAM的雙向數(shù)據(jù)選通（128K的× 32位× 4組雙速率同步圖形RAM的帶雙向數(shù)據(jù)選通）
文件頁數(shù)： 8/47頁
文件大?。?/td> 912K
代理商： KM432D5131
Target
16M DDR SGRAM
- 9 -
KM432D5131
Rev. 0.6 (Apr. 1998)
á
DEFINE SPECIAL FUNCTION(DSF)
The DSF controls the graphic applications of SGRAM. If DSF is tied to low, SGRAM functions are the same as SDRAM
functions. SGRAM can be used as an unified memory by the appropriate DSF command. All the graphic function mode
can be entered only by setting DSF high when issuing commands which otherwise would be normal SDRAM commands.
See the sessions below for the graphic functions that DSF control.
á
SPECIAL MODE REGISTER SET(SMRS)
There is a special mode register in DDR SGRAM. It is color register. This usage will be explained at "BLOCK WRITE"
session. When A6 and DSF goes high in the same cycle as CS, RAS, CAS and WE going low, load color register(LCR)
process is executed and the color register is filled with color data for associated DQ
′
s through the DQ pins. At the next
clock of LCR, a new commands can be issued. SMRS, compared with MRS, can be issued at the active state under the
condition that DQ
′
s are idle.
Special Mode Register Programmed with SMRS
Address
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Function
X
LC
X
Load Color Register
A
6
Function
0
Disable
1
Enable
Command
SMRS Cycle
SMRS
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ
′
s
Color
CK, CK
2
0
1
5
3
4
8
6
7
NOP
NOP
Load Color
Register
Block write is a feature allowing the simultaneous writing of consecutive 16 columns of data within a RAM device during
a single access cycle. During block write the data to be written comes from an internal "color" register. The block of col-
umn to be written is aligned on 16 column boundaries and is defined by the column address with the 4 LSB
Write command with DSF=High enables block write for the associated bank. A write command with DSF=Low enables
normal write for the associated bank. The block width is 16 column where column="n" bits for by "n" part. The color reg-
ister is the same width as the data port of the chip. The color register provides the data without column masking. So DQ
states are don
′
t cared. And Null Column Mask command with high state on DQs make no problem. DQS should toggle
once for valid data mask(DM) input. Block writes are always non-burst, independent of the burst length that has been
programmed into the mode register. Back to back block writes are allowed provided that the specified block write cycle
time(tBWC) is satisfied.
′
s ignored.
á
BLOCK WRITE
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