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參數(shù)資料
| 型號： | KM432D5131 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K x 32Bit x 4 Banks Double Data Rate Synchronous Graphic RAM with Bi-directional Data Strobe(128K x 32位 x 4 組雙速率同步圖形RAM帶雙向數(shù)據(jù)選通) |
| 中文描述： | 128K的x 32Bit的× 4銀行雙數(shù)據(jù)速率同步圖形RAM的雙向數(shù)據(jù)選通（128K的× 32位× 4組雙速率同步圖形RAM的帶雙向數(shù)據(jù)選通） |
| 文件頁數(shù)： | 7/47頁 |
| 文件大?。?/td> | 912K |
| 代理商： | KM432D5131 |
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Target
16M DDR SGRAM
- 8 -
KM432D5131
Rev. 0.6 (Apr. 1998)
The mode register stores the data for controlling the various operating modes of DDR SGRAM. It programs
addressing mode, burst length, test mode and various vendor specific options to make DDR SGRAM useful for variety of
different applications. The default value of the mode register is not defined, therefore the mode register must be written
after power up to operate the DDR SGRAM. The mode register is written by asserting low on
DDR SGRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address
pins A
0
~ A
8
and BA
0
, BA
1
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. One
clock cycle is requested to complete the write operation in the mode register. The mode register contents can be changed
using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The
mode register is divided into various fields depending on functionality. The burst length uses A
uses A
3
, CAS latency(read latency from column address) uses A
4
~ A
6
. A
7
is used for test mode. A
7
, A
8
, BA
0
and BA
1
must be set to low for normal DDR SGRAM operation. Refer to the table for specific codes for various burst length,
addressing modes and CAS latencies.
CAS latency,
CS, RAS, CAS and WE(The
0
~ A
2
, addressing mode
á
MODE REGISTER SET(MRS)
BA
1
BA
0
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
RFU
TM
CAS Latency
BT
Burst Length
Mode Register
CAS Latency
A
6
0
0
0
0
1
1
1
1
A
5
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
Latency
Reserve
Reserve
2
3
Reserve
Reserve
Reserve
Reserve
Burst Length
A
2
A
1
A
0
Burst Type
Sequential
Reserve
2
4
8
Reserve
Reserve
Reserve
Full page
Interleave
Reserve
2
4
8
Reserve
Reserve
Reserve
Reserve
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A
7
0
1
mode
Normal
Test
Burst Type
A
3
0
1
Type
Sequential
Interleave
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
MRS Cycle
Command
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum
t
RP
is required to issue MRS command.
0
CK, CK
Precharge
All Banks
NOP
NOP
MRS
NOP
NOP
NOP
2
0
1
5
3
4
8
6
7
Any
NOP
Command
t
RP
1 t
CK
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相關(guān)代理商/技術(shù)參數(shù) |
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