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參數(shù)資料
| 型號(hào)： | KM432D5131 |
| 廠(chǎng)商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128K x 32Bit x 4 Banks Double Data Rate Synchronous Graphic RAM with Bi-directional Data Strobe(128K x 32位 x 4 組雙速率同步圖形RAM帶雙向數(shù)據(jù)選通) |
| 中文描述： | 128K的x 32Bit的× 4銀行雙數(shù)據(jù)速率同步圖形RAM的雙向數(shù)據(jù)選通（128K的× 32位× 4組雙速率同步圖形RAM的帶雙向數(shù)據(jù)選通） |
| 文件頁(yè)數(shù)： | 2/47頁(yè) |
| 文件大?。?/td> | 912K |
| 代理商： | KM432D5131 |
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Target
16M DDR SGRAM
- 3 -
KM432D5131
Rev. 0.6 (Apr. 1998)
The KM432D5131 is 16,777,216 bits of hyper synchronous data rate Dynamic GRAM organized as 4 x 131,072 words by
32 bits, fabricated with SAMSUNG
′
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.144GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
3.3V
±
5% power supply for device operation
2.5V
±
5% power supply for I/O interface
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 2, 3 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
Full page burst length for sequential burst type only
Start address of the full page burst should be even
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
Data I/O transactions on both edges of Data strobe
Data input & output & DM are synchronized with DQS
á
GENERAL DESCRIPTION
á
FEATURES
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
8ms refresh period (1K cycle)
100pin TQFP package
Maximum clock frequency up to 143MHz
Maximum data rate up to 286Mbps/pin
Graphics Features
SMRS cycle.
-. Load color register
16 Columns Block Write.
Byte Masking with DM for Block Write operation is sup-
ported.
FOR 128K x 32Bit x 4 Bank DDR SGRAM
128K x 32Bit x 4 Banks Double Data Rate Synchronous Graphic RAM
with Bi-directional Data Strobe
á
ORDERING INFORMATION
Part NO.
Max Freq.
Interface
Package
KM432D5131TQ-G7
143MHz
SSTL
100 TQFP
KM432D5131TQ-G8
125MHz
100 TQFP
KM432D5131TQ-G0
100MHz
100 TQFP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM432S2020B | 1M x 32Bit x 2 Banks Synchronous DRAM(1M x 32位 x 2 組同步動(dòng)態(tài)RAM) |
| KM432S2030C | 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| KM432S2030CT-F6 | 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| KM432S2030CT-F7 | 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| KM432S2030CT-F8 | 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM432D5131TQ-G8 | 制造商:Samsung Semiconductor 功能描述: |
| KM432J | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:R. F. Molded Chokes |
| KM432S2030C | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| KM432S2030CT-F10 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| KM432S2030CT-F6 | 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
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