參數(shù)資料
型號： KM418RD4D
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
中文描述： 128/144Mbit RDRAM的256 × 16/18位× 2 * 16屬銀行直接RDRAMTM
文件頁數(shù)： 56/64頁
文件大?。?/td> 4052K
代理商： KM418RD4D
Page 53
KM416RD8AC(D)/KM418RD8AC(D)
Direct RDRAM
Rev. 1.01 Oct. 1999
Figure 58 also shows the combinational path connecting
SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read
data only). The t
PROP1
parameter specified this propagation
delay. The rise and fall times of SIO0 and SIO1 inputs must
be t
DR1
and t
DF1
, measured at the 20% and 80% levels. The
rise and fall times of SIO0 and SIO1 outputs are t
QR1
and
t
QF1
, measured at the 20% and 80% levels.
RSL - Domain Crossing Window
When read data is returned by the RDRAM, information
must cross from the receive clock domain (CFM) to the
transmit clock domain (CTM). The t
TR
parameter permits
the CFM to CTM phase to vary through an entire cycle; i.e.
there is no restriction on the alignment of these two clocks.
A second parameter t
DCW
is needed in order to describe how
the delay between a RD command packet and read data
packet varies as a function of the t
TR
value.
Figure 59 shows this timing for five distinct values of t
TR
.
Case A (t
TR
=0) is what has been used throughout this docu-
ment. The delay between the RD command and read data is
t
CAC
. As t
TR
varies from zero to t
CYCLE
(cases A through
E), the command to data delay is (t
CAC
-t
TR
). When the t
TR
value is in the range 0 to t
DCW,MAX
, the command to data
delay can also be (t
CAC
-t
TR
-t
CYCLE
). This is shown as cases
A’ and B’ (the gray packets). Similarly, when the t
TR
value
is in the range (t
CYCLE
+t
DCW,MIN
) to t
CYCLE
, the command
to data delay can also be (t
CAC
-t
TR
+t
CYCLE
). This is shown
as cases D’ and E’(the gray packets). The RDRAM will
work reliably with either the white or gray packet timing.
The delay value is selected at initialization, and remains
fixed thereafter.
Figure 59: RSL Transmit - Crossing Read Domains
CFM
COL
t
TR
CTM
DQA/B
DQA/B
t
TR
=0
t
CYCLE
Case A
t
TR
=0
Case A’
t
TR
CTM
DQA/B
DQA/B
t
TR
=t
DCW,MAX
Case B
t
TR
=t
DCW,MAX
Case B’
t
TR
CTM
DQA/B
t
TR
=0.5t
CYCLE
Case C
CTM
DQA/B
DQA/B
t
TR
=t
CYCLE
+t
DCW,MIN
Case D
t
TR
=t
CYCLE
+t
DCW,MIN
Case D’
CTM
DQA/B
DQA/B
t
TR
=t
CYCLE
Case E
t
TR
=t
CYCLE
Case E’
t
TR
t
TR
RD a1
Q(a1)
Q(a1)
Q(a1)
Q(a1)
t
CAC
-t
TR
t
CAC
-t
TR
-t
CYCLE
Q(a1)
Q(a1)
Q(a1)
Q(a1)
Q(a1)
t
CAC
-t
TR
t
CAC
-t
TR
+t
CYCLE
t
CAC
-t
TR
t
CAC
-t
TR
+t
CYCLE
t
CAC
-t
TR
t
CAC
-t
TR
-t
CYCLE
t
CAC
-t
TR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KM418RD8AC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM418RD8AC(D)-RG60 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM418RD8AC(D)-RK70 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM418RD8AC(D)-RK80 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
KM418RD8ACD-RK70 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
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