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參數(shù)資料
| 型號： | KM418RD2AD |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| 中文描述： | 128/144Mbit RDRAM的256 × 16/18位× 2 * 16屬銀行直接RDRAMTM |
| 文件頁數(shù)： | 39/64頁 |
| 文件大?。?/td> | 4052K |
| 代理商： | KM418RD2AD |
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Page 36
KM416RD8AC(D)/KM418RD8AC(D)
Direct RDRAM
Rev. 1.01 Oct. 1999
.
Figure 39: TPARM Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
TCDLY0
TCLS
TCAS
Read/write register.
Reset value is undefined.
TCAS1..0 - Specifies the t
CAS-C
core parameter in
t
CYCLE
units. This should be
“
10
”
(2
t
CYCLE
).
TCLS1..0 - Specifies the t
CLS-C
core parameter in
t
CYCLE
units. Should be
“
10
”
(2
t
CYCLE
).
TCDLY0 - Specifies the t
CDLY0-C
core parameter in
t
CYCLE
units. This adds a programmable delay to Q
(read data) packets, permitting round trip read delay to
all devices to be equalized. This field may be written
with the values
“
011
”
(3
t
CYCLE
) through
“
101
”
(5
t
CYCLE
).
Control Register: TPARM
Address: 048
16
The equations relating the core parameters to the
datasheet parameters follow:
t
CAS-C
= 2
t
CYCLE
t
CLS-C
= 2
t
CYCLE
t
CPS-C
= 1
t
CYCLE
Not programmable
t
OFFP
= t
CPS-C
+ t
CAS-C
+ t
CLS-C
- 1
t
CYCLE
= 4
t
CYCLE
t
RCD
= t
RCD-C
+ 1
t
CYCLE
- t
CLS-C
= t
RCD-C
- 1
t
CYCLE
t
CAC
= 3
t
CYCLE
+ t
CLS-C
+ t
CDLY0-C
+ t
CDLY1-C
(see table below for programming ranges)
011
011
101
100
TCDLY0
011
3t
CYCLE
3t
CYCLE
5t
CYCLE
4t
CYCLE
t
CDLY0-C
3t
CYCLE
010
001
010
010
TCDLY1
000
2
t
CYCLE
1
t
CYCLE
2
t
CYCLE
2
t
CYCLE
t
CDLY1-C
0
t
CYCLE
10
t
CYCLE
9
t
CYCLE
12
t
CYCLE
11
t
CYCLE
t
CAC
8
t
CYCLE
Figure 40: TFRM Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
TFRM3..0
Read/write register.
Reset value is undefined.
TFRM3..0 - Specifies the position of the framing point
in t
CYCLE
units. This value must be greater than or
equal to the t
FRM,MIN
parameter. This is the minimum
offset between a ROW packet (which places a device at
ATTN) and the first COL packet (directed to that
device) which must be framed. This field may be
written with the values
“
0111
”
(7
t
CYCLE
) through
“
1010
”
(10
t
CYCLE
). TFRM is usually set to the value
which matches the largest t
RCD,MIN
parameter (modulo
4
t
CYCLE
) that is present in an RDRAM in the memory
system. Thus, if an RDRAM with t
RCD,MIN
=
9
t
CYCLE
were present, then TFRM would be
programmed to 9
t
CYCLE
.
Control Register: TFRM
Address: 049
16
Figure 41: TRDLY Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCDLY1
Read/write register.
Reset value is undefined.
TCDLY1 - Specifies the value of the t
CDLY1-C
core
parameter in t
CYCLE
units. This adds a programmable
delay to Q (read data) packets, permitting round trip
read delay to all devices to be equalized. This field may
be written with the values
“
000
”
(0
t
CYCLE
) through
“
010”
(2
t
CYCLE
). Refer to Figure 39 for more details.
Control Register: TCDLY1
Address: 04a
16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM418RD2C | 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD2D | 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD32AC | 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD32AD | 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD32C | 128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM418RD2C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD2D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD32AC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD32AD | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
| KM418RD32C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128/144Mbit RDRAM 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM |
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