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參數(shù)資料
| 型號(hào)： | KM416S4031C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 16Bit x 4 Banks Synchronous DRAM with SSTL interface(1M x 16位 x4組同步動(dòng)態(tài)RAM（帶SSTL接口）) |
| 中文描述： | 100萬(wàn)× 16 × 4銀行同步DRAM接口與薩里衛(wèi)星技術(shù)有限公司（100萬(wàn)× 16位x4組同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶SSTL公司接口）） |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | KM416S4031C |
KM416S4031C
CMOS SDRAM
REV. 0 April 1998
Preliminary
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Veraion
Unit
Note
-7
-S
-8
Row active to row active delay
t
RRD
(min)
14
20
16
ns
1
RAS to CAS delay
t
RCD
(min)
21
20
24
ns
1
Row precharge time
t
RP
(min)
21
20
24
ns
1
Row active time
t
RAS
(min)
48
50
50
ns
1
t
RAS
(max)
100
us
Row cycle time
t
RC
(min)
70
70
80
ns
1
Last data in to new col. address delay
t
CDL
(min)
1
CLK
2
Last data in to row precharge
t
RDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. address to col. address delay
t
CCD
(min)
1
CLK
3
Number of valid output data
CAS latency=3
2
-
2
ea
4
CAS latency=2
1
1
1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Notes :
Vtt = 0.45 * V
DDQ
50
Output
C
LOAD
= 30pF
Z0 = 50
(Fig. 1) Output load circuit
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, 3.43V
±
0.5%, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
Input reference voltage
0.45 * V
DDQ
V
Input signal maximum peak swing
2.0
V
Input signal minimum slew rate
1.0
V/ns
AC input levels (Vih/Vil)
V
REF
+0.4/V
REF
-0.4
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
Vtt
V
Output load condition
See Fig. 1
V
REF
= 0.45 * V
DDQ
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