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參數(shù)資料
| 型號(hào)： | KM416S4031C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 16Bit x 4 Banks Synchronous DRAM with SSTL interface(1M x 16位 x4組同步動(dòng)態(tài)RAM（帶SSTL接口）) |
| 中文描述： | 100萬× 16 × 4銀行同步DRAM接口與薩里衛(wèi)星技術(shù)有限公司（100萬× 16位x4組同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器（帶SSTL公司接口）） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 62K |
| 代理商： | KM416S4031C |
KM416S4031C
CMOS SDRAM
REV. 0 April 1998
Preliminary
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
PIN CONFIGURATION
(Top view)
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
V
REF
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
SS
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System clock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
11
, Column address : CA
0
~ CA
7
A
0
~ A
11
Address
BA
0
~ BA
1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
L(U)DQM
Data input/output mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ
0
~
15
Data input/output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power supply/ground
Power and ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
V
REF
Reference voltage
Reference voltage for inputs.
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| KM416S8030BN | 128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| KM416S8030B | 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM416S8030 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Synchronous DRAM |
| KM416S8030B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| KM416S8030BN | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| KM416S8030BN-G/FH | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
| KM416S8030BN-G/FL | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb SDRAM Shrink TSOP 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL |
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