參數(shù)資料
型號(hào)： KM416C4004C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 4M x 16bit CMOS Dynamic RAM with Extended Data Out
中文描述： 4米× 16位的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器的擴(kuò)展數(shù)據(jù)輸出
文件頁(yè)數(shù)： 9/36頁(yè)
文件大?。?/td> 946K
代理商： KM416C4004C
KM416C4004C,
KM416C4104C
CMOS DRAM
t
CWL
is specified from W falling edge to the earlier CAS rising edge.
t
CSR
is referenced to the earlier CAS falling edge before RAS transition low.
t
CHR
is referenced to the later CAS rising edge after RAS transition low.
t
DS
is specified for the earlier CAS falling edge and
t
DH
is specified by the later CAS falling edge in early write cycle.
t
ASC
≥
6ns, Assume t
T
= 2.0ns
If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes
high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
If
t
RASS
≥
100us, then RAS precharge time must use
t
RPS
instead of
t
RP
.
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
t
CSR
t
CHR
RAS
LCAS
UCAS
t
DS
t
DH
LCAS
UCAS
DQ0 ~ DQ15
Din
22.
21.
20.
19.
18.
17.
16.
23.
24.
相關(guān)PDF資料
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