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參數資料
| 型號： | KM29V040T |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 8 Bit NAND Flash Memory(512K x 8位 NAND閃速存儲器) |
| 中文描述： | 為512k × 8位NAND閃存（為512k × 8位的NAND閃速存儲器） |
| 文件頁數： | 19/21頁 |
| 文件大?。?/td> | 223K |
| 代理商： | KM29V040T |
KM29V040T, KM29V040IT
FLASH MEMORY
19
Figure 7. RESET Operation
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a frame program, erase or read seek
completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or
a random read is begin after address loading. It returns to high when the internal controller has finished the operation. The pi n is an
open-drain driver thereby allowing two or more R/ B outputs to be Or-tied. An appropriate pull-up resister is required for proper opera-
tion and the value may be calculated by following equation.
RESET
The device offers a reset feature, executed by writing FFH to the command register. When the device is in Busy state during the
read, program or erase mode, the reset operation will abort these operation. In the case of Reset during Program or Erase opera-
tions, the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The d evice
enters the Read mode after completion of Reset operation as shown Table 3. If the device is already in reset state a new reset com-
mand will not be accepted to by the command register. The R/ B pin transitions to low for t
RST
after the Reset command is written.
Reset command is not necessarily for normal device operation. Refer to Figure 7 below.
After Power-up
After Reset
Operation Mode
Read
Read
FFH
I/O
0
~
7
R/B
Rp =
V
CC
R/B
open drain output
Device
GND
V
CC
(Max.) - V
OL
(Max.)
I
OL
+
Σ
I
L
=
Note*
8mA
+
Σ
I
L
where I
L
is the sum of the input currents of all devices tied to the
R/B pin.
Table3. Device Status
Note* KM29N040 ; 5.1V
KM29V040 ; 3.2V
KM29W040A ; 5.1V when Vcc=3.6V~5.5V
3.2V when Vcc=3.0V~3.6V
t
RST
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