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| 型號： | KIT33394DWBEVB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 25/44頁 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MC33394 8X PWR SPLY |
| 標準包裝： | 1 |
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33394
31
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Figure 18. Error Amplifier Two–Pole–Two–Zero
Compensation Network
–
+
C2
R2
C1
C3
R1
R3
R
Ref
E/A
VCOMP
VPRE_S
U1
The process of determining the right compensation
components starts with analysis of the open loop (modulator)
transfer function, which has to be determined and plotted into
the Bode plot (see Figure 19). The modulator DC gain can be
determined as follows:
ADC +
Vin
DVe
Where Ve is the maximum change of the Error Amplifier
voltage to change the duty cycle from 0 to 100 percent (Ve =
2.6 V at Vbat =14 V).
As can be seen from Figure 19, the buck converter
modulator transfer function has a double complex pole
caused by the output L–C filter. Its corner frequency can be
calculated as:
fp(LC) +
1
2
p LCo
This double pole exhibits a —40dB per decade rolloff and
a —180 degree phase shift.
Another point of interest in the modulator’s transfer
function is the zero caused by the ESR of the output
capacitor Co and the capacitance of the output capacitor
itself:
fz(ESR) +
1
2
pRESRCo
The ESR zero causes +20dB per decade gain increase,
and +90 degree phase shift.
Once the open loop transfer function is determined, the
appropriate compensation can be applied in order to obtain
the required closed loop cross over frequency and phase
margin (~60 degree) — refer to Figure 18 and Figure 19.
Figure 19 shows the 33394 Switching Regulator modulator
gain–phase plot, E/A gain–phase plot, closed loop
gain–phase plot, and the E/A compensation circuit. The
frequency fxo is the required cross–over frequency of the
buck regulator.
In order to achieve the best performance (the highest
bandwidth) and stability of the voltage–mode controlled buck
PWM regulator the two–pole–two–zero type of compensation
was selected — see Figure 19 for the compensated Error
Amplifier Bode plot, and Figure 18 for the compensation
network. The two compensating zeros and their positive
phase shift (2 x +90 degree) associated with this type of
compensation can counteract the negative phase shift
caused by the double pole of the modulator’s output filter.
Figure 19. Bode Plot of the Buck Regulator
A1
100 k
10 k
1000
100
10
11 M
–60
–40
–20
0
20
40
60
80
f (Hz)
GAIN
(dB)
–360
–270
–180
–90
0
90
PHASE
(deg)
100 k
10 k
1000
100
10
11 M
f (Hz)
MODULATOR
CLOSED LOOP (overall)
ERROR AMPLIFIER
MODULATOR
CLOSED LOOP (overall)
ERROR
AMPLIFIER
fp1
fp2
A2
fZ(ESR)
fZ2
fZ1
fp(LC)
Ifxo
The frequency of the compensating poles and zeros can
be calculated from the following expressions:
fz1 +
1
2
pR2C2
fz2 +
1
2
p(R1 ) R3)C3
[
1
2
pR1C3
fp1 +
1
2
pR3C3
fp2 +
C1 ) C2
2
pR2C1C2
[
1
2
pR2C1
and the required absolute gain is:
A1 +
R2
R1
A2 +
R2(R1 ) R3)
R1R3
[
R2
R3
Refer to Application Schematic Diagram (Figure 20) and
Table 2 for the 33394 switcher component values.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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