參數(shù)資料
型號: KFM2G16Q2M-DED5
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: MuxOneNAND FLASH MEMORY
中文描述: MuxOneNAND閃存
文件頁數(shù): 8/124頁
文件大小: 1550K
代理商: KFM2G16Q2M-DED5
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
8
MuxOneNAND
is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This device includes con-
trol logic, a NAND Flash array, and 5KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering (BootRAM) and
4KB for data buffering (DataRAM), split between 2 independent buffers. It has a x16 Host Interface and a random access time speed
of ~76ns.
The device operates up to a maximum host-driven clock frequency of 54MHz for synchronous reads at Vcc(or Vccq. Refer to chapter
4.2)
with minimum 4-clock latency. Below 40MHz it is accessible with minimum 3-clock latency. Appropriate wait cycles are deter-
mined by programmable read latency.
MuxOneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter
register. The device includes one block-sized OTP (One Time Programmable) area that can be used to increase system security or
to provide identification capabilities.
1.6
General Overview
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