參數(shù)資料
型號: KFM2G16Q2M-DED5
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: MuxOneNAND FLASH MEMORY
中文描述: MuxOneNAND閃存
文件頁數(shù): 118/124頁
文件大?。?/td> 1550K
代理商: KFM2G16Q2M-DED5
MuxOneNAND1G(KFM1G16Q2M-DEB5)
MuxOneNAND2G(KFN2G16Q2M-DEB5)
FLASH MEMORY
118
Synchronous Mode Using the INT Pin
When operating synchronously, INT is tied directly to a Host GPIO.
An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of
using the INT pin.
Host
MuxOneNAND
Asynchronous Mode Using the INT Pin
When configured to operate in an asynchronous mode, /CE and /AVD of the MuxOneNAND are tied to /CE of the Host. CLK is tied to
the Host Vss (Ground). /RDY is tied to a no-connect. /OE of the MuxOneNAND and Host are tied together and INT is tied to a GPIO.
RDY
OE
CLK
CE
RDY
OE
CLK
CE
AVD
AVD
GPIO
INT
Host
MuxOneNAND
N.C
OE
Vss
CE
RDY
OE
CLK
CE
AVD
GPIO
INT
This can be configured in either a synchronous mode or an asynchronous mode.
INT
Command
7.1.2 Polling the Interrupt Register Status Bit
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