參數(shù)資料
型號： KAC-1310
廠商： Electronic Theatre Controls, Inc.
英文描述： 1280 (H) x 1024 (V) SXGA CMOS Image Sensor
中文描述： 1280（高）x 1024（五）SXGA CMOS圖像傳感器
文件頁數(shù)： 38/76頁
文件大?。?/td> 759K
代理商： KAC-1310
IMAGE SENSOR SOLUTIONS
38
IMAGE SENSOR SOLUTIONS
K A C - 1 3 1 0 R e v 4 w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 E m a i l : i m a g e r s @ k o d a k . c o m
Repeated START Signal
A Repeated START signal is a START signal
generated without first generating a STOP signal
to terminate the communication. This is used by
the master to communicate with another slave or
with the same slave in a different mode
(transmit/receive mode) without releasing the bus.
As shown in
Figure 26
,
page
39
, a Repeated
START signal is being used during the read cycle
and to redirect the data transfer from a write cycle
(master transmits the register address to the
slave) to a read cycle (slave transmits the data
from the designated register to the slave).
I
2
C Bus Clocking and synchronization
Open drain outputs are used on the SCLK outputs
of all master and slave devices so that the clock
can be synchronized and stretched using wire-
AND logic. This means that the slowest device
will keep the bus from going faster than it is
capable of receiving or transmitting data.
After the master has driven SCLK from High to
Low, all the slaves drive SCLK Low for the
required period that is needed by each slave
device and then releases the SCLK bus. If the
slave SCLK Low period is greater than the master
SCLK Low period, the resulting SCLK bus signal
Low period is stretched. Therefore, synchronized
clocking occurs since the SCLK is held low by the
device with the longest Low period. Also, this
method can be used by the slaves to slow down
the bit rate of a transfer. The master controls the
length of time that the SCLK line is in the High
state. The data on the SDATA line is valid when
the master switches the SCLK line from a High to
a Low. Slave devices may hold the SCLK low
after completion of one byte transfer (9 bits). In
such case, it halts the bus clock and forces the
master clock into wait states until the slave
releases the SCLK line.
Register Write
Writing the KAC-1310 registers is accomplished
with the following I
C transactions (see
Figure 25
page
36
):
Master transmits a START
Master transmits the KAC-1310 Slave Calling
Address with “WRITE” indicated (BYTE=66
h
,
102
d
, 01100110
b
)
KAC-1310 slave sends acknowledgment by
forcing the SDATA Low during the 9
th
clock, if
the Calling Address was received
Master transmits the KAC-1310 Register
Address
KAC-1310 slave sends acknowledgment by
forcing the SDATA Low during the 9
th
clock
after receiving the Register Address
Master transmits the data to be written into the
register at the previously received Register
Address
KAC-1310 slave sends acknowledgment by
forcing the SDATA Low during the 9
clock
after receiving the data to be written into the
Register Address
The Master transmits STOP to end the write
cycle
Register Read
Reading the KAC-1310 registers is accomplished
with the following I
C transactions (see
Figure 26
,
page
39
):
Master transmits a START
Master transmits the KAC-1310 Slave Calling
Address with “WRITE” indicated (BYTE=66
h
,
102
d
, 01100110
b
)
KAC-1310 slave sends acknowledgment by
forcing the SDATA Low during the 9
th
clock, if
the Calling Address was received
Master transmits the KAC-1310 Register
Address
KAC-1310 slave sends acknowledgment by
forcing the SDATA Low during the 9
th
clock
after receiving the Register Address
Master transmits a Repeated START
Master transmits the KAC-1310 Slave Calling
Address with “READ” indicated (BYTE = 67
h
,
103
d
, 01100111
b
)
KAC-1310 slave sends acknowledgment by
forcing the SDATA Low during the 9
th
clock, if
the Calling Address was received
At this point, the KAC-1310 transitions from a
“Slave-Receiver” to a “Slave-Transmitter”
KAC-1310 sends the SCLK and the Register
Data contained in the Register Address that
was previously received from the master;
KAC-1310 transitions to slave-receiver
Master does not send an acknowledgment
(NAK)
Master transmits STOP to end the read cycle
相關(guān)PDF資料
PDF描述
KAF-1001E 1024(H) x 1024(V) Pixel Enhanced Response Full-Frame CCD Image Sensor Performance Specification
KAF-1602E Replacement for Texas Instruments part number SN74LS164N. Buy from authorized manufacturer Rochester Electronics.
KaLNA3S.04R Ka Band Low Noise Amplifier(工作頻率從33GHz到36GHz的低噪聲Ka波段功率放大器)
KAQW214 PHOTO MOS RELAYS
KAQW414A HIGH VOLTAGE, PHOTO MOS RELAY
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KAC-15 功能描述:保險絲 600V 15A Semiconductor RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險絲類型:Fast Acting 保險絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485
KAC-150 功能描述:保險絲 600V 150A Semiconductor RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險絲類型:Fast Acting 保險絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485
KAC-17.5 制造商:COOPER 制造商全稱:Cooper Bussmann, Inc. 功能描述:High Speed Fuses
KAC-17-1/2 功能描述:保險絲 600V 17.5A Semiconductor RoHS:否 制造商:Littelfuse 產(chǎn)品:Surface Mount Fuses 電流額定值:0.5 A 電壓額定值:600 V 保險絲類型:Fast Acting 保險絲大小/組:Nano 尺寸:12.1 mm L x 4.5 mm W 安裝風(fēng)格: 端接類型:SMD/SMT 系列:485
KAC-17-1-2 制造商:Cooper Bussmann 功能描述:FUSE 17.5A 600V 2PIN - Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*