參數(shù)資料
型號: KAC-1310
廠商: Electronic Theatre Controls, Inc.
英文描述: 1280 (H) x 1024 (V) SXGA CMOS Image Sensor
中文描述: 1280(高)x 1024(五)SXGA CMOS圖像傳感器
文件頁數(shù): 32/76頁
文件大?。?/td> 759K
代理商: KAC-1310
IMAGE SENSOR SOLUTIONS
32
IMAGE SENSOR SOLUTIONS
K A C - 1 3 1 0 R e v 4 w w w . k o d a k . c o m / g o / i m a g e r s 5 8 5 - 7 2 2 - 4 3 8 5 E m a i l : i m a g e r s @ k o d a k . c o m
Figure 21: CFRS Default Row Sync Waveforms
SOF
TRIGGER
VCLK
HCLK
Standard Frame
Timing (Figure 18)
r
r
r
r
r
r
r
T = (cint
d
+ 1)*Row Time
Figure 22: Single Frame Capture Mode (SFRS)
Symbol
Characteristic
Min
Typ
Max
Unit
f
max
MCLK maximum frequency
1
10
20
MHz
t
htrig
TRIGGER hold time w.r.t. MCLK
3.5
-
9
ns
t
sutrig
TRIGGER setup time w.r.t. MCLK
3.0
-
8.5
ns
t
dsof
MCLK to SOF delay time
8
13
21.5
ns
t
dvclk
MCLK to VCLK delay time
8.5
13.5
22
ns
t
drhclk
Rising edge of MCLK to rising edge of HCLK delay time
7.5
13
22
ns
t
dfhclk
Falling edge of MCLK to falling edge of HCLK delay time
3
5
10.5
ns
t
dadc
MCLK to ADC[9:0] delay time
8
13
21.5
ns
t
dblank
MCLK to BLANK delay time
8
13
21.5
ns
Table 8: Pixel Data Bus and Sync Timing Specification
MCLK
Pixel Array Values
1
Row Time = vcw
d
+ 39
c
row 16
c
c
row 17
c
2
3
4
5
6
7
8
1
2
3
3
3
1
2
3
1
1
1
2
3
1
1
SOF
VCLK
HCLK
ADC[9:0]
Valid Pixel Data
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