參數(shù)資料
型號: K6R3024V1D
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128K x 24 Bit High-Speed CMOS Static RAM(3.3V Operating)
中文描述: 128K的× 24位高速CMOS靜態(tài)RAM(3.3V的工作)
文件頁數(shù): 6/9頁
文件大?。?/td> 172K
代理商: K6R3024V1D
K6R3024V1D
CMOS SRAM
Revision 1.0
December 2001
- 6 -
for AT&T
NOTES
(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
9. CS represents CS
1
, CS
2
and CS
3
in this data sheet. CS
2
as of opposite polarity to CS
1
and CS
3.
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
CS
Address
OE
Data ou
t
t
AA
t
OLZ
t
LZ(4,5)
t
OHZ
t
RC
t
OE
t
CO
t
PU
t
PD
Valid Data
t
HZ(3,4,5)
50%
50%
V
CC
Current
I
CC
I
SB
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
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