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參數(shù)資料
| 型號： | K6F1616U6M-F |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 16 bit Super Low Power and Low Voltage Full CMOS Static RAM |
| 中文描述： | 100萬× 16位超低功耗和低電壓的CMOS靜態(tài)RAM全 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 176K |
| 代理商： | K6F1616U6M-F |
K6F1616U6M Family
Preliminary
CMOS SRAM
Revision 0.1
November 2000
5
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): C
L
=100pF+1TTL
C
L
=30pF+1TTL
AC CHARACTERISTICS
(Vcc=2.7~3.3V, T
A
=-40 to 85
°
C)
Parameter List
Symbol
Speed Bins
Units
55ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO1
, t
CO2
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
LB, UB valid to data output
t
BA
-
55
-
70
ns
Chip select to low-Z output
t
LZ1
, t
LZ2
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
LB, UB enable to low-Z output
t
BLZ
10
-
10
-
ns
Output hold from address change
t
OH
10
-
10
-
ns
Chip disable to high-Z output
t
HZ1
, t
HZ2
0
20
0
25
ns
OE disable to high-Z output
t
OHZ
0
20
0
25
ns
UB, LB disable to high-Z output
t
BHZ
0
20
0
25
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW1
, t
CW2
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
50
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
20
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
LB, UB valid to end of write
t
BW
45
-
60
-
ns
C
L
1)
1. Including scope and jig capacitance
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.8V
R
2
2)
R
1
2)
V
TM
3)
DATA RETENTION CHARACTERISTICS
1.
1) CS
1
≥
Vcc-0.2V, CS
2
≥
Vcc-0.2V(CS
1
controlled) or
2) 0
≤
CS
2
≤
0.2V(CS
2
controlled) or
3) LB=UB
≥
Vcc-0.2V, CS
2
≥
Vcc-0.2V(LB/UB controlled)
2. Typical value are measured at T
A
=25
°
C and not 100% tested.
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
VDR
CS
1
≥
Vcc-0.2V
1)
, V
IN
≥
0V
1.5
-
3.3
V
Data retention current
IDR
Vcc=1.5V, CS
1
≥
Vcc-0.2V
1)
, V
IN
≥
0V
-
1.0
2)
15
μ
A
Data retention set-up time
tSDR
See data retention waveform
0
-
-
ns
Recovery time
tRDR
tRC
-
-
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