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參數(shù)資料
| 型號： | K4R571669D |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256/288Mbit RDRAM(D-die) |
| 中文描述： | 256/288Mbit的RDRAM（深模） |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 311K |
| 代理商： | K4R571669D |
Direct RDRAM
K4R571669D/K4R881869D
Page 17
Version 1.4 July 2002
Capacitance and Inductance
Table 17: RSL Pin Parasitics
Symbol
Parameter and Conditions - RSL pins
Min
Max
Unit
Figure
L
I
RSL effective input inductance
@ t
CYCLE
=1.875ns
-
3.5
nH
Figure 63
RSL effective input inductance
@ t
CYCLE
=2.5ns
-
4.0
L
12
Mutual inductance between any DQA or DQB RSL signals.
-
0.2
nH
Figure 63
Mutual inductance between any ROW or COL RSL signals.
-
0.6
nH
L
I
Difference in L
I
value between any RSL pins of a single device.
-
1.8
nH
Figure 63
C
I
RSL effective input capacitance
a
@ t
CYCLE
=1.875ns
2.0
2.3
pF
Figure 63
RSL effective input capacitance
a
@ t
CYCLE
=2.5ns
2.0
2.4
C
12
Mutual capacitance between any RSL signals.
-
0.1
pF
Figure 63
C
I
Difference in C
I
value between average of {CTM, CTMN,
CFM, CFMN} and any RSL pins of a single device.
-
0.06
pF
Figure 63
R
I
RSL effective input resistance
@ t
CYCLE
=1.875ns
4
10
Figure 63
RSL effective input resistance
@ t
CYCLE
=2.5ns
4
15
a. This value is a combination of the device IO circuitry and package capacitances
Table 18: CMOS Pin Parasitics
Symbol
Parameter and Conditions - CMOS pins
Min
Max
Unit
Figure
L
I ,CMOS
CMOS effective input inductance
8.0
nH
Figure 63
C
I ,CMOS
CMOS effective input capacitance (SCK,CMD)
a
1.7
2.1
pF
C
I ,CMOS,SIO
CMOS effective input capacitance (SIO1, SIO0)
a
-
7.0
pF
a. This value is a combination of the device IO circuitry and package capacitances.
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