參數(shù)資料
型號(hào): K4R571669D
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256/288Mbit RDRAM(D-die)
中文描述: 256/288Mbit的RDRAM(深模)
文件頁(yè)數(shù): 18/20頁(yè)
文件大?。?/td> 311K
代理商: K4R571669D
Direct RDRAM
K4R571669D/K4R881869D
Page 16
Version 1.4 July 2002
Absolute Maximum Ratings
Note*) Component : refer to T
J,
Θ
JC
RIMM: refre to T
PLATE, MAX
I
DD
- Supply Current Profile
Table 14: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
V
I,ABS
Voltage applied to any RSL or CMOS pin with respect to Gnd
- 0.3
V
DD
+0.3
V
V
DD,ABS
, V
DDA,ABS
Voltage on VDD and VDDA with respect to Gnd
- 0.5
V
DD
+1.0
V
T
STORE
Storage temperature
- 50
100
°
C
T
MIN
Minimum operation temperature
0
Note*
°
C
Table 15: Supply Current Profile
I
DD
value
RDRAM Power State and Steady-State Transaction Rates
a
Min
Max
(1066MHz, -
32P/-32/-35)
Max
(800MHz,
-40/-45)
Unit
I
DD,PDN
Device in PDN, self-refresh enabled and INIT.LSR=0.
-
6000
6000
μ
A
I
DD,NAP
Device in NAP.
-
4
4
mA
I
DD,STBY
Device in STBY. This is the average for a device in STBY with (1) no
packets on the Channel, and (2) with packets sent to other devices.
-
100
80
mA
I
DD,REFRESH
Device in STBY and refreshing rows at the t
REF,MAX
period.
-
100
80
mA
I
DD,ATTN
Device in ATTN. This is the average for a device in ATTN with (1) no
packets on the Channel, and (2) with packets sent to other devices.
-
150
120
mA
I
DD,ATTN-W
Device in ATTN. ACT command every 8t
CYCLE
, PRE command every
8t
CYCLE
, WR command every 4
t
CYCLE
, and data is 1100..1100
-
790(x18)
b
730(x16)
620(x18)
575(x16)
mA
I
DD,ATTN-R
Device in ATTN. ACT command every 8t
CYCLE
, PRE command every
8
t
CYCLE
, RD command every 4
t
CYCLE
, and data is 1111..1111
c
-
700(x18)
650(x16)
560(x18)
530(x16)
mA
a. CMOS interface consumes power in all power states.
b. x18/x16 RDRAM data width.
c. This does not include the I
OL
sink current. The RDRAM dissipates I
OL
V
OL
in each output driver when a logic one is driven.
Table 16: Supply Current at Initialization
Symbol
Parameter
Allowed Range of t
CYCLE
V
DD
Min
Max
Unit
I
DD,PWRUP,D
I
DD
from power -on to SETR
1.875ns to 2.5ns
V
DD,MIN
-
200
a
mA
I
DD,SETR,D
I
DD
from SETR to CLRR
1.875ns to 2.5ns
V
DD,MIN
-
332
mA
a. The supply current will be 150mA when t
CYCLE
is in the range 15ns to 1000ns.
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