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參數(shù)資料
| 型號： | K4N51163QC-ZC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Mbit gDDR2 SDRAM |
| 中文描述： | 512MB的GDDR2 SDRAM的 |
| 文件頁數(shù)： | 57/64頁 |
| 文件大小： | 1420K |
| 代理商： | K4N51163QC-ZC |
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- 57 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
CMD
CKE
CMD
CKE
T0
T3
T5
T6
T7
T8
T9
T1
T2
T4
T10
CMD
CKE
CMD
CKE
CKE can go to low one clock after an Active command
PR or
PRA
MRS or
EMRS
REF
ACT
tMRD
Active command to power down entry
Precharge/Precharge all command to power down entry
MRS/EMRS command to power down entry
CK
CK
CKE can go to low one clock after a Precharge or Precharge all command
CKE can go to low one clock after an Auto-refresh command
T11
DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this data sheet. If CKE asynchronously drops “LOW”
during any valid operation DRAM is not guaranteed to preserve the contents of array. If this event occurs, memory controller must sat-
isfy DRAM timing specification tDelay before turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised
“HIGH” again. DRAM must be fully re-initialized (steps 4 thru 13) as described in initialization sequence. DRAM is ready for normal oper-
ation after the initialization sequence. See AC timing parametric table for tDelay specification.
Asynchronous CKE Low Event
Refresh command to power down entry
tCK
CK
CK#
tDelay
CKE
CKE asynchronously drops low
Clocks can be turned
off after this point
Stable clocks
tIS
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相關(guān)代理商/技術(shù)參數(shù) |
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| K4N51163QC-ZC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit gDDR2 SDRAM |
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| K4N51163QC-ZC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit gDDR2 SDRAM |
| K4N51163QC-ZC36 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit gDDR2 SDRAM |
| K4N51163QG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:Graphic Memory |
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