參數(shù)資料
型號(hào): K4N51163QC-ZC
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512Mbit gDDR2 SDRAM
中文描述: 512MB的GDDR2 SDRAM的
文件頁數(shù): 25/64頁
文件大?。?/td> 1420K
代理商: K4N51163QC-ZC
- 25 -
Rev 1.5 Oct. 2005
512M gDDR2 SDRAM
K4N51163QC-ZC
*1 : The rest bits in EMRS(2) is reserved for future use and all bits except A0, A1, A2, A7and BA0, BA1, must be programmed
to 0 when setting the mode register during initialization.
.
*2 : If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be
loast if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command
is issued. PASR is supported from the device of 90nm technology(512Mb C-die).
*1 : All bits in EMRS(3) except BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the
mode register during initialization.
Address Field
Extended Mode Register(2)
BA1
BA0
MRS mode
0
0
MRS
0
1
EMRS(1)
1
0
EMRS(2)
1
1
EMRS(3): Reserved
A7
High Temperature Self-Refresh Rate Enable
1
Enable
0
Disable
A2
A1
A0 Partial Array Self Refresh for 4 Banks
0
0
0
Full array
0
0
1
Half Array(BA[1:0]=00&01)
0
1
0
Quarter Array(BA[1:0]=00)
0
1
1
Not defined
1
0
0
3/4 array(BA[1:0]=01, 10&11)
1
0
1
Half array(BA[1:0]=10&11)
1
1
0
Quarter array(BA[1:0]=11)
1
1
1
Not defined
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
0
*1
0
*1
SRF
0
*1
PSAR
*2
Address Field
Extended Mode Register(3)
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
1
0
*1
EMRS (2) Programming
EMRS (3) Programming : Reserved
*1
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