參數(shù)資料
型號： K4E641612D
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： CMOS DRAM
中文描述： 的CMOS內(nèi)存
文件頁數(shù)： 1/36頁
文件大小： 397K
代理商： K4E641612D
CMOS DRAM
K4E661612D,K4E641612D
Industrial Temperature
T h i s i s a f a m i l y o f 4 , 1 9 4 , 3 0 4 x 1 6 b i t E x t e n d e d D a t a O u t M o d e C M O S D R A M s . E x t e n d e d D a t a O u t M o d e o f f e r s h i g h s p e e d r a n d o m
a c c e s s o f m e m o r y c e l l s w i t h i n t h e s a m e r o w . R e f r e s h c y c l e ( 4 K R e f . o r 8 K R e f . ) , a c c e s s t i m e ( - 4 5 , - 5 0 o r - 6 0 ) , p o w e r c o n s u m p t i o n ( Nor-
mal or Low power) are optional features of this family. All of this family have C A S -before-R A S refresh, R A S - o n l y r e f r e s h a n d H i d d e n
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated
u s i n g S a m s u n g
′
s a d v a n c e d C M O S p r o c e s s t o r e a l i z e h i g h b a n d - w i d t h , l o w p o w e r c o n s u m p t i o n a n d h i g h r e l i a b i l i t y .
E x t e n d e d D a t a O u t M o d e o p e r a t i o n
2 C A S B y t e / W o r d R e a d / W r i t e o p e r a t i o n
C A S-before-R A S refresh capability
R A S-only and Hidden refresh capability
Fast parallel test mode capability
Self-refresh capability (L-ver only)
L V T T L ( 3 . 3 V ) c o m p a t i b l e i n p u t s a n d o u t p u t s
Early Write or output enable controlled write
J E D E C S t a n d a r d p i n o u t
A v a i l a b l e i n P l a s t i c T S O P ( I I ) p a c k a g e s
+3.3V
±
0 . 3 V p o w e r s u p p l y
Industrial Temperature operating
( - 4 0 ~ 8 5
°
C
)
Control
Clocks
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc
Vss
D Q 0
to
D Q 7
A0~A12
(A0~A11)*1
A0~A8
(A0~A9)*1
Memory Array
4,194,304 x 16
Cells
S A M S U N G E L E C T R O N I C S C O . , L T D .
reserves the right to
change products and specifications without notice.
4M x 16bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Note) *1 : 4K Refresh
S
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
D Q
8
to
DQ15
O E
Row Decoder
Column Decoder
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Part Identification
- K 4 E 6 6 1 6 1 2 D - T I / P ( 3 . 3 V , 8 K R e f . )
- K 4 E 6 4 1 6 1 2 D - T I / P ( 3 . 3 V , 4 K R e f . )
FEATURES
Refresh Cycles
Part
N O .
Refresh
cycle
R e f r e s h t i m e
N o r m a l
L-ver
K 4 E 6 6 1 6 1 2 D *
8 K
6 4 m s
1 2 8 m s
K 4 E 6 4 1 6 1 2 D
4 K
Unit :
m W
* A c c e s s m o d e & R A S o n l y r e f r e s h m o d e
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
C A S - b e f o r e -R A S & H i d d e n r e f r e s h m o d e
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Active Power Dissipation
S p e e d
8 K
4 K
- 4 5
3 2 4
4 6 8
- 5 0
2 8 8
4 3 2
- 6 0
2 5 2
3 9 6
Performance Range
S p e e d
t
RAC
t
CAC
t
RC
t
HPC
-45
4 5 n s
1 2 n s
7 4 n s
1 7 n s
-50
5 0 n s
1 3 n s
8 4 n s
2 0 n s
-60
6 0 n s
1 5 n s
1 0 4 n s
2 5 n s
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