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參數(shù)資料
| 型號(hào)： | IT8687R |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GT 35C 35#12 SKT PLUG |
| 中文描述： | 初步規(guī)范v0.6版本 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 85K |
| 代理商： | IT8687R |
IT8687R
Preliminary V0.6
Specifications subject to Change without Notice
I/O Buffer Chip
ITPA-PN-98012 Joseph. Mar. 06
1
1. Features
n
Contains six (6) line drivers (1488)and ten (10)
line receivers(1489)
n
Supports two (2) RS-232 serial ports
n
Very low power consumption (150mW)
n
Supports one (1) crystal oscillator clock generator
n
Four power supply inputs:0V,5V,-12V,+12V
n
High voltage CMOS process
n
48-pin SSOP package
2. General Description
IT8687R integrates six (6) line drivers, ten (10) line
receivers, one ISA signal encoder, one (1) UART
signal-mixing control logic, and one 24/48 MHz
clock generator. The ISA signals; (1) SA12, SA13,
SA14, SA15,
DACK0#,
DACK3#, AEN, RESET are encoded into three (3)
signals -- RAD0, RAD1, RAD2. 16 UART interface
DACK1#,
DACK2#,
signals are encoded into UIF0, UIF1, UIF2, UIF3,
UIF4 to minimize the pin count and the package
cost. This low power consumption chip is designed
to serve as an interface between data terminal
equipment and data communication equipment in
conformance with the EIA standard RS-232
specifications.
3. Pin Configuration
UIF4/LTX1
UIF3/LRTS1
UIF2/LRLSD1
UIF1/LRX1
UIF0/LDTR1
GND
CLKOUT
X2
X1
RAD2/LDSR1
RAD1/LCTS1
RAD0/LRI1
VCC
DACK3#/LRLSD2
DACK2#/LRX2
DACK1#
DACK0#/LTX2
AEN/LDSR2
GND
SA15/LCTS2
SA14/LRI2
SA13/LRTS2
SA12/LDTR2
RESET
MODE
VDD
TX1
RTS1
DTR1
VSS
NC
RLSD1
RX1
DSR1
CTS1
RI1
RLSD2
RX2
DSR2
CTS2
RI2
NC
VSS
TX2
RTS2
DTR2
VDD
NC
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