Specifications ispLSI 1032EA USE ispMA CH 4A5 FOR NEW 5V DESIGNS Maximum GRP Delay vs GLB Loads GLB Load ispLSI 1032EA-200 ispLSI 1032EA-170" />
參數(shù)資料
型號: ISPLSI 1032EA-170LT100
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 5/16頁
文件大?。?/td> 0K
描述: IC PLD ISP 64I/O 5NS 100TQFP
標準包裝: 90
系列: ispLSI® 1000EA
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 5.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
邏輯元件/邏輯塊數(shù)目: 32
門數(shù): 6000
輸入/輸出數(shù): 64
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-TQFP(14x14)
包裝: 托盤
其它名稱: ISPLSI1032EA-170LT100
13
Specifications ispLSI 1032EA
USE
ispMA
CH
4A5
FOR
NEW
5V
DESIGNS
Maximum GRP Delay vs GLB Loads
GLB Load
ispLSI 1032EA-200
ispLSI 1032EA-170
ispLSI 1032EA-125
ispLSI 1032EA-100
3
4
1
8
16
32
GRP
Delay
(ns)
4
2
GRP/GLB/1032EA
1
Power Consumption
Power consumption in the ispLSI 1032EA device de-
pends on two primary factors: the speed at which the
device is operating, and the number of product terms
used. Figure 4 shows the relationship between power
and operating speed.
0127/1032EA
Icc can be estimated for the ispLSI 1032EA using the following equation:
Icc = 20mA + (# of PTs * .52) + (# of nets * Max Freq * .003)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating
conditions and the program in the device, the actual Icc should be verified.
fmax (MHz)
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
160
140
120
100
200
0
50
100
150
200
250
I CC
(mA)
220
ispLSI 1032EA
180
240
260
Figure 4. Typical Device Power Consumption vs fmax
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