參數(shù)資料
型號： ISP1761BE,518
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù)： 157/164頁
文件大?。?/td> 767K
代理商： ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
91 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
2. Set the corresponding bits of the OTG Interrupt Enable Rise and OTG Interrupt
Enable Fall registers.
3. Set bit OTG_IRQ_E of the HcInterruptEnable register (bit 10).
4. Set bit GLOBAL_INTR_EN of the HW Mode Control register (bit 0).
When an interrupt is generated on HC_IRQ, perform these steps in the interrupt service
routine to get the related OTG status:
1. Read the HcInterrupt register. If OTG_IRQ (bit 10) is set, then step 2.
2. Read the OTG Interrupt Latch register. If any of the bits 0 to 4 are set, then step 3.
3. Read the OTG Status register.
The OTG state machine routines are called when any of the inputs is changed. These
inputs come from either OTG registers (hardware) or application program (software). The
outputs of the state machine include control signals to the OTG register (for hardware)
and states or error codes (for software).
The ISP1761 can be congured in OTG mode or in pure host or peripheral mode.
Programming the ISP1761 in OTG mode is done by conguring bit 10 of the OTG control
register. This will enable OTG-specic mechanisms controlled by the OTG control register
bits.
When the OTG protocol is not implemented by the software, the ISP1761 can be used as
a host or a peripheral. In this case, bit 10 of the OTG control register will be set to logic 0.
The host or peripheral functionality is determined by bit 7 of the OTG Control register.
Programming of OTG registers is done by a SET and RESET scheme. An OTG register
has two parts: a 16-bit SET and a 16-bit RESET. Writing logic 1 in a certain position to the
SET-type dedicated 16-bit register part will set the respective bit to logic 1 while writing
logic 1 to the RESET-type 16-bit dedicated register will change the corresponding bit to
logic 0.
9.5 OTG controller registers
Table 79.
OTG controller-specic register overview
Address
Register
Reset value
References
037Xh to 038Xh OTG registers
-
Table 80.
Address mapping of registers: 32-bit data bus mode
Address
Byte 3
Byte 2
Byte 1
Byte 0
Device ID registers
0370h
Product ID (read only)
Vendor ID (read only)
OTG Control register
0374h
OTG Control (clear)
OTG Control (set)
OTG Interrupt registers
0378h
reserved
OTG Status (read only)
037Ch
OTG Interrupt Latch (clear)
OTG Interrupt Latch (set)
0380h
OTG Interrupt Enable Fall (clear)
OTG Interrupt Enable Fall (set)
0384h
OTG Interrupt Enable Rise (clear)
OTG Interrupt Enable Rise (set)
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