參數(shù)資料
型號: ISP1761BE,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT425-1, LQFP-128
文件頁數(shù): 14/164頁
文件大?。?/td> 767K
代理商: ISP1761BE,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
109 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.6 Data ow registers
10.6.1 Endpoint Index register
The Endpoint Index register selects a target endpoint for register access by the
microcontroller. The register consists of 1 byte, and the bit allocation is shown in
The following registers are indexed:
Buffer Length
DcBufferStatus
Control Function
Data Port
Table 108. DcInterruptEnable - Device Controller Interrupt Enable register (address 0214h)
bit description
Bit
Symbol
Description
31 to 26
-
reserved
25
EP7TX
Logic 1 enables interrupt from the indicated endpoint.
24
EP7RX
Logic 1 enables interrupt from the indicated endpoint.
23
EP6TX
Logic 1 enables interrupt from the indicated endpoint.
22
EP6RX
Logic 1 enables interrupt from the indicated endpoint.
21
EP5TX
Logic 1 enables interrupt from the indicated endpoint.
20
EP5RX
Logic 1 enables interrupt from the indicated endpoint.
19
EP4TX
Logic 1 enables interrupt from the indicated endpoint.
18
EP4RX
Logic 1 enables interrupt from the indicated endpoint.
17
EP3TX
Logic 1 enables interrupt from the indicated endpoint.
16
EP3RX
Logic 1 enables interrupt from the indicated endpoint.
15
EP2TX
Logic 1 enables interrupt from the indicated endpoint.
14
EP2RX
Logic 1 enables interrupt from the indicated endpoint.
13
EP1TX
Logic 1 enables interrupt from the indicated endpoint.
12
IEP1RX
Logic 1 enables interrupt from the indicated endpoint.
11
IEP0TX
Logic 1 enables interrupt from the control IN endpoint 0.
10
IEP0RX
Logic 1 enables interrupt from the control OUT endpoint 0.
9
-
reserved
8
IEP0SETUP
Logic 1 enables interrupt for the set-up data received on endpoint 0.
7
IEVBUS
Logic 1 enables interrupt for VBUS sensing.
6
IEDMA
Logic 1 enables interrupt on detecting a DMA status change.
5
IEHS_STA
Logic 1 enables interrupt on detecting a high-speed status change.
4
IERESM
Logic 1 enables interrupt on detecting a resume state.
3
IESUSP
Logic 1 enables interrupt on detecting a suspend state.
2
IEPSOF
Logic 1 enables interrupt on detecting a pseudo SOF.
1
IESOF
Logic 1 enables interrupt on detecting an SOF.
0
IEBRST
Logic 1 enables interrupt on detecting a bus reset.
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