參數(shù)資料
型號: ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 81/150頁
文件大?。?/td> 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
81 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
15.2.4
HcLSThreshold register (R/W: 11H/91H)
The HcLSThreshold register contains an 11-bit value used by the HC to determine
whether to commit to the transfer of a maximum of 8-byte LS packet before the EOF.
Neither the HC nor the HCD is allowed to change this value.
Table 53
shows the bit
allocation of the register.
Code (Hex): 11
read
Code (Hex): 91
write
Table 52:
Bit
31 to 16
15 to 0
HcFmNumber register: bit description
Symbol
Description
reserved
FN[15:0]
FrameNumber:
This is incremented when HcFmRemaining is
reloaded. It needs to be rolled over to 0H after FFFFH. When the
USBOperational state is entered, this is incremented automatically.
The content needs to be written to HCCA after the HC has
incremented the FrameNumber (FN) at each frame boundary and
sent an SOF. However, the content needs to be written before
the HC reads the
fi
rst Endpoint Descriptor (ED) in that frame. After
writing to HCCA, the HC needs to set the StartofFrame (SF) in
HcInterruptStatus.
Table 53:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcLSThreshold register: bit allocation
31
30
29
28
27
26
25
24
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23
22
21
20
19
18
17
16
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9
-
-
8
15
14
13
12
11
10
reserved
-
-
5
LST[10:8]
1
R/W
1
-
-
7
-
-
6
-
-
4
-
-
3
1
0
R/W
2
R/W
0
LST[7:0]
0
0
1
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 54:
Bit
31 to 11
10 to 0
HcLSThreshold register: bit description
Symbol
Description
reserved
LST[10:0]
LSThreshold:
Contains a value that is compared to the
FrameRemaining (FR)
fi
eld before a low-speed transaction is
initiated. The transaction is started only if FrameRemaining
(FR)
this
fi
eld. The value is calculated by the HCD, which
considers transmission and set-up overhead.
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