參數(shù)資料
型號: ISP1362BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 59/150頁
文件大?。?/td> 647K
代理商: ISP1362BD
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
59 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
The DC in the ISP1362 will remain in the suspend state for at least 5 ms, before
responding to external wake-up events, such as global resume, bus traf
fi
c, CS active
or LOW pulse on the D_SUSPEND/D_WAKEUP pin.
Figure 27
shows a typical timing diagram for the DC suspend and resume operations.
In
Figure 27
:
A
indicates the point at which the USB bus goes to the idle state.
B
after detecting the suspend interrupt, set and clear the GOSUSP bit in the Mode
register.
C
indicates resume condition, which can be a resume signal from the host, a LOW
pulse on the D_SUSPEND/D_WAKEUP pin, or a LOW pulse on the CS pin.
D
indicates remote wake-up. The ISP1362 will drive a K-state on the USB bus for
10 ms after the D_SUSPEND/D_WAKEUP pin goes LOW or the CS pin goes LOW.
13.5.2
Resume conditions
Wake-up from the suspend state is initiated either by the USB host or by the
application:
USB host: drives a K-state on the USB bus (global resume)
Application: remote wake-up using a LOW pulse on pin D_SUSPEND/D_WAKEUP
or a LOW pulse on pin CS (if enabled using bit WKUPCS of the
DcHardwareCon
fi
guration register).
The steps of a wake-up sequence are as follows:
Fig 27. Suspend and resume timing.
004aaa483
INT2
> 5 ms
suspend
interrupt
USB BUS
GOSUSP (bit)
CS
idle state
10 ms
K-state
> 3 ms
1.8 ms to
2.2 ms
0.5 ms to
3.5 ms
resume
interrupt
A
D
B
C
D_SUSPEND/D_WAKEUP
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