參數(shù)資料
型號: ISP1183BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù): 38/62頁
文件大?。?/td> 295K
代理商: ISP1183BS
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
38 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.3.3
DMA Counter register (R/W: F3H/F2H)
This command accesses the DMA Counter register, which consists of 2 bytes. The bit
allocation is given in
Table 34
. Writing to the register sets the number of bytes for a
DMA transfer. Reading the register returns the number of remaining bytes in the
current transfer. A bus reset will not change the programmed bit values.
The internal DMA counter is automatically reloaded from the DMA Counter register
when DMA is re-enabled (DMAEN = 1). For more details, see
Section 13.3.2
.
Code (hex): F2/F3 —
write or read DMA Counter register
Transaction —
write or read 2 bytes
13.4 General commands
13.4.1
Endpoint Error Code (R: A0H–AFH)
This command returns the status of the last transaction of the selected endpoint, as
stored in the Error Code register. Each new transaction overwrites the previous status
information. The bit allocation of the Error Code register is shown in
Table 36
.
3
DMASTART
Writing logic 1 starts DMA transfer. Logic 0 forces the end of an
ongoing DMA transfer. Reading this bit indicates whether DMA
is started (0 = DMA stopped, 1 = DMA started). This bit is
cleared by a bus reset.
reserved
Selects the DMA burst length:
2
1 to 0
-
BURSTL[1:0]
00 —
single-cycle mode (1 byte)
01 —
burst mode (4 bytes)
10 —
burst mode (8 bytes)
11 —
burst mode (16 bytes).
Bus reset value: unchanged.
Table 33:
Bit
DMA Configuration register: bit description
…continued
Symbol
Description
Table 34:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DMA Counter register: bit allocation
15
14
13
12
DMACRH[7:0]
0
R/W
4
DMACRL[7:0]
0
R/W
11
10
9
8
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 35:
Bit
15 to 8
7 to 0
DMA Counter register: bit description
Symbol
Description
DMACRH[7:0]
DMA Counter register (high byte)
DMACRL[7:0]
DMA Counter register (low byte)
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