參數(shù)資料
型號(hào): ISP1183BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù): 31/62頁
文件大?。?/td> 295K
代理商: ISP1183BS
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
31 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Code (hex): C2/C3 —
write or read Interrupt Enable register
Transaction —
write or read 4 bytes
Table 22:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Interrupt Enable register: bit allocation
31
30
29
28
27
26
25
24
reserved
0
0
0
0
0
0
0
0
R/W
23
IEP14
0
R/W
15
IEP6
0
R/W
7
reserved
0
R/W
R/W
22
IEP13
0
R/W
14
IEP5
0
R/W
6
SP_IEEOT
0
R/W
R/W
21
IEP12
0
R/W
13
IEP4
0
R/W
5
IEPSOF
0
R/W
R/W
20
IEP11
0
R/W
12
IEP3
0
R/W
4
IESOF
0
R/W
R/W
19
IEP10
0
R/W
11
IEP2
0
R/W
3
IEEOT
0
R/W
R/W
18
IEP9
0
R/W
10
IEP1
0
R/W
2
IESUSP
0
R/W
R/W
17
IEP8
0
R/W
9
IEP0IN
0
R/W
1
IERESM
0
R/W
R/W
16
IEP7
0
R/W
8
IEP0OUT
0
R/W
0
IERST
0
R/W
Table 23:
Bit
31 to 24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
Interrupt Enable register: bit description
Symbol
Description
-
reserved; must write logic 0
IEP14
Logic 1 enables interrupts from endpoint 14.
IEP13
Logic 1 enables interrupts from endpoint 13.
IEP12
Logic 1 enables interrupts from endpoint 12.
IEP11
Logic 1 enables interrupts from endpoint 11.
IEP10
Logic 1 enables interrupts from endpoint 10.
IEP9
Logic 1 enables interrupts from endpoint 9.
IEP8
Logic 1 enables interrupts from endpoint 8.
IEP7
Logic 1 enables interrupts from endpoint 7.
IEP6
Logic 1 enables interrupts from endpoint 6.
IEP5
Logic 1 enables interrupts from endpoint 5.
IEP4
Logic 1 enables interrupts from endpoint 4.
IEP3
Logic 1 enables interrupts from endpoint 3.
IEP2
Logic 1 enables interrupts from endpoint 2.
IEP1
Logic 1 enables interrupts from endpoint 1.
IEP0IN
Logic 1 enables interrupts from the control IN endpoint.
IEP0OUT
Logic 1 enables interrupts from the control OUT endpoint.
-
reserved
SP_IEEOT
Logic 1 enables interrupt on detection of a short packet.
IEPSOF
Logic 1 enables 1 ms interrupts on detection of Pseudo SOF.
IESOF
Logic 1 enables interrupt on SOF detection.
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