參數(shù)資料
型號(hào): ISP1183BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Low-power Universal Serial Bus interface device with DMA
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù): 32/62頁
文件大?。?/td> 295K
代理商: ISP1183BS
Philips Semiconductors
ISP1183
Low-power USB interface device with DMA
Product data
Rev. 01 — 24 February 2004
32 of 62
9397 750 11804
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13.1.6
Reset Device (F6H)
This command resets the ISP1183 in the same way as an external hardware reset
through input RESET_N. All registers are initialized to their reset values.
Code (hex): F6 —
reset the device
Transaction —
none
13.2 Data flow commands
Data flow commands are used to manage the data transmission between USB
endpoints and the system microcontroller. Much of the data flow is initiated through
an interrupt to the microcontroller. The data flow commands are used to access the
endpoints and determine whether the endpoint FIFOs contain valid data.
Remark:
The IN buffer of an endpoint contains input data
for
the host. The OUT
buffer receives output data
from
the host.
13.2.1
Endpoint Buffer (R/W: 10H, 12H–1FH/01H–0FH)
This command accesses endpoint FIFO buffers for reading or writing. First, the buffer
pointer is reset to the beginning of the buffer. Following the command, a maximum of
(N + 2) bytes can be written or read, N representing the size of the endpoint buffer.
After each read or write action, the buffer pointer is automatically incremented by one
(8-bit bus width).
In DMA access, the first two bytes (the packet length) are skipped: transfers start at
the third byte of the endpoint buffer. When reading, the ISP1183 can detect the last
byte through the EOP condition. When writing to a bulk or interrupt endpoint, the
endpoint buffer must be completely filled before sending data to the host.
Remark:
Reading data after a Write Endpoint Buffer command or writing data after a
Read Endpoint Buffer command data will cause unpredictable behavior of the
ISP1183.
Code (hex): 01 to 0F —
write (control IN, endpoints 1 to 14)
Code (hex): 10, 12 to 1F —
read (control OUT, endpoints 1 to 14)
Transaction —
write or read maximum (N + 2) bytes (isochronous endpoint:
N
1023, bulk or interrupt endpoint: N
64)
The data in the endpoint FIFO must be organized as shown in
Table 24
. Examples of
endpoint FIFO access are given in
Table 25
.
3
2
1
0
IEEOT
IESUSP
IERESM
IERST
Logic 1 enables interrupt on EOT detection.
Logic 1 enables interrupt on detection of a suspend state.
Logic 1 enables interrupt on detection of a resume state.
Logic 1 enables interrupt on detection of a bus reset.
Table 23:
Bit
Interrupt Enable register: bit description
…continued
Symbol
Description
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