參數(shù)資料
型號(hào): ISP1181DGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: INDUCTOR 4.7NH +-.3NH 0402 SMD
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, TSSOP-48
文件頁數(shù): 5/69頁
文件大?。?/td> 1655K
代理商: ISP1181DGG
Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
5 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
6.2 Pin description
Table 2:
Symbol
[1]
V
CC(5.0)
REGGND
V
reg(3.3)
Pin description for TSSOP48
Pin
Type
1
-
2
-
3
-
Description
supply voltage (3.0 to 5.5 V)
voltage regulator ground supply
regulated supply voltage (3.3 V
±
10%) from internal
regulator; used to connect decoupling capacitor and pull-up
resistor on D
+
line;
Remark:
Cannot be used to supply external devices.
USB D
connection (analog)
USB D
+
connection (analog)
V
BUS
sensing input
GoodLink LED indicator output (open-drain, 8 mA); the LED
is default ON, blinks OFF upon USB traffic; to connect an
LED use a 330
series resistor;
wake-up input (edge triggered, LOW to HIGH); generates a
remote wake-up from ‘suspend’ state
‘suspend’ state indicator output (4 mA); used as power switch
control output (active LOW) for powered-off application or as
resume signal to the CPU (active HIGH) for powered-on
application
End-Of-Transfer input (programmable polarity, see
Table 23
);
used by the DMA controller to force the end of a DMA transfer
by the ISP1181
DMA request output (4 mA; programmable polarity, see
Table 23
); signals to the DMA controller that the ISP1181
wants to start a DMA transfer
DMA acknowledge input (programmable polarity, see
Table 23
); used by the DMA controller to signal the start of a
DMA transfer requested by the ISP1181
DMA write strobe input; used only in bus configuration
mode 1 (separate PIO and DMA ports)
DMA read strobe input; used only in bus configuration
mode 1 (separate PIO and DMA ports)
interrupt output; programmable polarity (active HIGH or LOW)
and signalling (level or pulse); see
Table 23
I/O ready output; a LOW level indicates that ISP1181 is
processing a previous command or data and is not ready for
the next PIO command or data transfer; a HIGH level signals
that ISP1181 will complete a PIO data transfer; applies only
to a PIO port or a PIO port shared with a DMA port
bus configuration selector; see
Table 3
bus configuration selector; see
Table 3
bit 15 of D[15:0]; bi-directional data line (slew-rate controlled
output, 4 mA)
bit 14 of D[15:0]; bi-directional data line (slew-rate controlled
output, 4 mA)
D
D
+
V
BUS
GL
4
5
6
7
AI/O
AI/O
I
O
WAKEUP
8
I
SUSPEND
9
O
EOT
10
I
DREQ
11
O
DACK
12
I
SDWR
13
I
SDRD
14
I
INT
15
O
READY
16
O
BUS_CONF1
BUS_CONF0
DATA15
17
18
19
I
I
I/O
DATA14
20
I/O
相關(guān)PDF資料
PDF描述
ISP1183 Low-power Universal Serial Bus interface device with DMA
ISP1183BS Low-power Universal Serial Bus interface device with DMA
ISP1301 Universal Serial Bus On-The-Go transceiver
ISP1301BS Universal Serial Bus On-The-Go transceiver
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ISP1183BS,157 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20