參數(shù)資料
型號: ISP1181DGG
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: INDUCTOR 4.7NH +-.3NH 0402 SMD
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
封裝: 6.10 MM, PLASTIC, TSSOP-48
文件頁數(shù): 18/69頁
文件大?。?/td> 1655K
代理商: ISP1181DGG
Philips Semiconductors
ISP1181
Full-speed USB interface
Objective specification
Rev. 01 — 13 March 2000
18 of 69
9397 750 06896
Philips Electronics N.V. 2000. All rights reserved.
11. Suspend and resume
11.1 Suspend conditions
The ISP1181 detects a USB ‘suspend’ status in the following cases:
A J-state is present on the USB bus for 3 ms
V
BUS
is lost (weak pull-up/down on D
+
and D
)
SoftConnect is disabled by clearing bit SOFTCT in the Mode Register, with
external pull-ups disabled by EXTPUL = 0 in the Hardware Configuration Register.
In this situation ISP1181 is effectively disconnected from the USB bus.
ISP1181 will remain in ‘suspend’ state for at least 5 ms, before responding to external
wake-up events such as global resume, bus traffic, wake-up on CS or WAKEUP. The
typical timing is shown in
Figure 5
.
Bus-powered devices that are suspended must not consume more than 500
μ
A of
current. This is achieved by shutting down the power to system components or
supplying them with a reduced voltage.
ISP1181 can either be in powered-on or powered-off mode during ‘suspend’ state.
This is controlled by bit PWROFF in the Hardware Configuration Register. A full
explanation of these modes is given in
Section 11.1.1
and
Section 11.1.2
.
The steps leading up to ‘suspend’ status are as follows:
1. Upon detection of a ‘wake-up’ to ‘suspend’ transition ISP1181 sets bit SUSPND
in the Interrupt Register. This will generate an interrupt if bit IESUSP in the
Interrupt Enable Register is set.
2. When the firmware detects a ‘suspend’ condition it must prepare all system
components for ‘suspend’ state:
a. All signals connected to ISP1181 must enter appropriate states to meet the
power consumption requirements of ‘suspend’ state.
b. All input pins of ISP1181 must have a CMOS logic 0 or logic 1 level. Pin
settings differ for powered-on and powered-off application.
3. In the interrupt service routine the firmware must check the current status of the
USB bus. When bit BUSTATUS in the Interrupt Register is logic 0, the USB bus
has left ‘suspend’ mode and the process must be aborted. Otherwise, the next
step can be executed.
Fig 5.
Typical suspend timing.
handbook, full pagewidth
MGS949
WAKEUP
suspend
>5 ms
start detection of
wake-up conditions
相關(guān)PDF資料
PDF描述
ISP1183 Low-power Universal Serial Bus interface device with DMA
ISP1183BS Low-power Universal Serial Bus interface device with DMA
ISP1301 Universal Serial Bus On-The-Go transceiver
ISP1301BS Universal Serial Bus On-The-Go transceiver
ISP1362 Single-chip Universal Serial Bus On-The-Go controller
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