參數(shù)資料
型號: ISP1161ABD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 94/134頁
文件大?。?/td> 587K
代理商: ISP1161ABD
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
94 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
Unchanged by a bus reset.
13.1.4
DcHardwareConfiguration register (R/W: BBH/BAH)
This command is used to access the DcHardwareConfiguration register, which
consists of 2 bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in
Table 82
. A bus reset will not change any
of the programmed bit values.
The DcHardwareConfiguration register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB —
write/read DcHardwareConfiguration register
Transaction —
write/read 1 word
Table 80:
Bit
Symbol
Reset
Access
DcMode register: bit allocation
7
DMAWD
0
[1]
R/W
6
5
4
3
2
1
0
reserved
0
R/W
GOSUSP
0
R/W
reserved
0
R/W
INTENA
0
[1]
R/W
DBGMOD
0
[1]
R/W
reserved
0
[1]
R/W
SOFTCT
0
[1]
R/W
Table 81:
Bit
7
DcMode register: bit description
Symbol
Description
DMAWD
Logic 1 selects 16-bit DMA bus width (bus configuration
modes 0 and 2). Logic 0 selects 8-bit DMA bus width. Bus reset
value: unchanged.
-
reserved
GOSUSP
Writing logic 1 followed by logic 0 will activate ‘suspend’ mode.
-
reserved
INTENA
Logic 1 enables all DC interrupts. Bus reset value: unchanged;
for details, see
Section 8.6.3
.
DBGMOD
Logic 1 enables debug mode, where all NAKs and errors will
generate an interrupt. Logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints).
Bus reset value: unchanged.
-
reserved
SOFTCT
Logic 1 enables SoftConnect (see
Section 7.5
). This bit is
ignored if EXTPUL = 1 in the DcHardwareConfiguration register
(see
Table 82
). Bus reset value: unchanged.
6
5
4
3
2
1
0
Table 82:
Bit
Symbol
Reset
Access
DcHardwareConfiguration register: bit allocation
15
14
reserved
EXTPUL
0
0
R/W
R/W
13
12
11
10
9
8
NOLAZY
1
R/W
CLKRUN
0
R/W
CLKDIV[3:0]
0
0
1
1
R/W
R/W
R/W
R/W
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