參數(shù)資料
型號: ISP1161ABD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus single-chip host and device controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 37/134頁
文件大小: 587K
代理商: ISP1161ABD
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
37 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.5.1
Time domain behavior
In example 1 (
Figure 30
), the microprocessor is fast enough to read back and
download a scenario before the next interrupt. Note that on the ISO interrupt of
frame N:
The ISO packet for frame N + 1 will be written
The AT packet for frame N + 1 will be written.
In example 2 (
Figure 31
), the microprocessor is still busy transferring the AT data
when the ISO interrupt of the next frame (N + 1) is raised. As a result, there will be no
AT traffic in frame N + 1. The HC does not raise an AT interrupt in frame N + 1. The
AT part is simply postponed until frame N + 2. On the AT N + 2 interrupt, the transfer
mechanism is back to normal operation. This simple mechanism ensures, among
other things, that Control transfers are not dropped systematically from the USB in
case of an overloaded microprocessor.
In example 3 (
Figure 32
), the ISO part is still being written while the Start of Frame
(SOF) of the next frame has occurred. This will result in undefined behavior for the
ISO data on the USB bus in frame N + 1 (depending on if the exact timing data is
corrupted or not). The HC should not raise an AT interrupt in frame N + 1.
Fig 30. HC time domain behavior: example 1.
MGT954
(frame N)
(frame N
+
1)
(frame N
+
2)
(frame N
+
3)
read ISO_A(N
1) write ISO_A(N
+
1)
SOF
read AT(N)
write AT(N
+
1)
AT
interrupt
traffic
on USB
ISO
interrupt
Fig 31. HC time domain behavior: example 2.
MGT955
(frame N)
(frame N
+
1)
(frame N
+
2)
(frame N
+
3)
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