參數(shù)資料
型號(hào)： ISP1161ABD
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù)： 84/134頁
文件大?。?/td> 587K
代理商： ISP1161ABD
Philips Semiconductors
ISP1161A
Full-speed USB single-chip host and device controller
Product data
Rev. 03 — 23 December 2004
84 of 134
9397 750 13962
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11.4.2
Resume conditions
A wake-up from the suspend state is initiated either by the USB host or by the
application:
USB host
: drives a K-state on the USB bus (global resume)
Application
: remote wake-up through a HIGH level on input WAKEUP or a LOW
level on input CS, if enabled using bit WKUPCS in the DcHardwareConfiguration
register. Wake-up on CS will work only if V
BUS
is present.
The steps of a wake-up sequence are as follows:
1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the
clock signals are routed to all internal circuits of the ISP1161A.
2. The SUSPEND output is deasserted, and bit RESUME in the DcInterrupt register
is set. This will generate an interrupt if bit IERESM in the DcInterruptEnable
register is set.
3. Maximum 15 ms after starting the wake-up sequence, the ISP1161A DC
resumes its normal functionality.
4. In case of a remote wake-up, the ISP1161A DC drives a K-state on the USB bus
for 10 ms.
5. Following the deassertion of output SUSPEND, the application restores itself and
other system components to the normal operating mode.
6. After wake-up, the internal registers of the ISP1161A DC are write-protected to
prevent corruption by inadvertent writing during power-up of external
components. The firmware must send an Unlock Device command to the
ISP1161A DC to restore its full functionality.
11.4.3
Control bits in suspend and resume
Table 69:
Register
DcInterrupt
Summary of control bits
Bit
SUSPND
BUSTATUS
Function
a transition from awake to the suspend state was detected
monitors USB bus status (logic 1 = suspend); used when
interrupt is serviced
a transition from suspend to the resume state was detected
enables output INT to signal the suspend state
enables output INT to signal the resume state
enables SoftConnect pull-up resistor to USB bus
a HIGH-to-LOW transition enables the suspend state
selects internal (SoftConnect) or external pull-up resistor
enables wake-up on LOW level of input CS
selects powered-off mode during the suspend state
sending data AA37H unlocks the internal registers for
writing after a resume
RESUME
IESUSP
IERESM
SOFTCT
GOSUSP
EXTPUL
WKUPCS
PWROFF
all
DcInterrupt
Enable
DcMode
DcHardware
Configuration
DcUnlock
相關(guān)PDF資料
PDF描述
ISP1161ABM Full-speed Universal Serial Bus single-chip host and device controller
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1161ABD,118 功能描述:USB 接口集成電路 DO NOT USE ORDER ISP1161A1BD RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161ABD,151 功能描述:USB 接口集成電路 DO NOT USE ORDER ISP1161A1BD RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161ABD,157 功能描述:USB 接口集成電路 DO NOT USE ORDER ISP1161A1BD RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1161ABD-S 功能描述:IC USB HOST CTRL FULL-SPD 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
ISP1161ABD-T 功能描述:IC USB HOST CTRL FULL-SPD 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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