參數(shù)資料
型號: ISP1160BM
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Embedded Universal Serial Bus Host Controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 59/88頁
文件大?。?/td> 2044K
代理商: ISP1160BM
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 04 — 04 July 2003
59 of 88
9397 750 11371
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
10.4.3
HcTransferCounter register (R/W: 22H/A2H)
This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer,
the number of bytes being read or written to the Isochronous Transfer List (ITL) or
Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a
DMA transfer, the number of bytes must be written into this register as well. However,
for this counter to be read into the DMA counter, the HCD must set bit 2
(DMACounterSelect) of the HcDMAConfiguration register. The counter value for ATL
must not be greater than 1000H, and for ITL it must not be greater than 800H. When
the byte count of the data transfer reaches this value, the HC will generate an internal
EOT signal to set bit 2 (AllEOTInterrupt) of the Hc
μ
PInterrupt register, and also
update the HcBufferStatus register.
Code (Hex): 22 —
read
Code (Hex): A2 —
write
10.4.4
Hc
μ
PInterrupt register (R/W: 24H/A4H)
All the bits in this register will be active on power-on reset. However, none of the
active bits will cause an interrupt on the interrupt pin (INT) unless they are set by the
respective bits in the Hc
μ
PInterruptEnable register, and together with bit 0 of the
HcHardwareConfiguration register.
2
DMACounter
Select
0 —
DMA counter not used. External EOT must be used
1 —
enables the DMA counter for DMA transfer.
HcTransferCounter register must be filled with non-zero values for
DREQ to be raised after bit DMA Enable is set.
0 —
ITL buffer RAM selected for ITL data
1
ITL_ATL_
DataSelect
1 —
ATL buffer RAM selected for ATL data
0 —
read from the HC FIFO buffer RAM
0
DMARead
WriteSelect
1 —
write to the HC FIFO buffer RAM
Table 39:
Bit
HcDMAConfiguration register: bit description
…continued
Symbol
Description
Table 40:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcTransferCounter register: bit allocation
15
14
13
12
Counter value
0
R/W
4
Counter value
0
R/W
11
10
9
8
0
0
0
0
0
0
0
R/W
7
R/W
6
R/W
5
R/W
3
R/W
2
R/W
1
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 41:
Bit
15 to 0
HcTransferCounter register: bit description
Symbol
Description
Counter
value
The number of data bytes to be read to or written from RAM.
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