參數(shù)資料
型號(hào): ISP1160BM
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 總線控制器
英文描述: Embedded Universal Serial Bus Host Controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁(yè)數(shù): 15/88頁(yè)
文件大?。?/td> 2044K
代理商: ISP1160BM
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 04 — 04 July 2003
15 of 88
9397 750 11371
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
There are two groups of interrupts represented by group 1 and group 2 in
Figure 13
.
A pair of registers control each group.
Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus
register). On occurrence of any of these events, the corresponding bit would be set to
logic 1; and if the corresponding bit in the HcInterruptEnable register is also logic 1,
the 6-input OR gate would output a logic 1. This output is AND-ed with the value of
MIE (bit 31 of HcInterruptEnable). Logic 1 at the AND gate will cause the OPR bit in
the Hc
μ
PInterrupt register to be set to logic 1.
Group 1 contains six possible interrupt events, one of which is the output of group 2
interrupt sources. The Hc
μ
PInterrupt and Hc
μ
PInterruptEnable registers work in the
same way as the HcInterruptStatus and HcInterruptEnable registers in the interrupt
group 2. The output from the 6-input OR gate is connected to a latch, which is
controlled by InterruptPinEnable (bit 0 of the HcHardwareConfiguration register).
In the event in which the software wishes to temporarily disable the interrupt output of
the ISP1160 Host Controller, the following procedure should be followed:
1. Make sure that the InterruptPinEnable bit in the HcHardwareConfiguration
register is set to logic 1.
2. Clear all bits in the Hc
μ
PInterrupt register.
3. Set the InterruptPinEnable bit to logic 0.
Fig 13. HC interrupt logic.
004aaa102
S
A
A
O
H
HcμPInterrupt
register
HcInterruptEnable
register
HcInterruptStatus
register
C
RHSC
FNO
UE
RD
SF
SO
RHSC
FNO
UE
RD
SF
SO
MIE
OR
S
A
A
O
H
HcμPInterruptEnable
register
C
OR
LATCH
INT
group 2
InterruptPinEnable
HcHardwareConfiguration
register
g
LE
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