參數(shù)資料
型號(hào): ISP1160BD-S
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù): 38/88頁(yè)
文件大小: 394K
代理商: ISP1160BD-S
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
43 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.1.6
HcInterruptDisable register (R/W: 05H/85H)
Each disable bit in the HcInterruptDisable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is
coupled with the HcInterruptEnable register. Thus, writing a logic 1 to a bit in this
register clears the corresponding bit in the HcInterruptEnable register, whereas
writing a logic 0 to a bit in this register leaves the corresponding bit in the
HcInterruptEnable register unchanged. On a read, the current value of the
HcInterruptEnable register is returned.
Code (Hex): 05 — read
Code (Hex): 85 — write
Table 17:
HcInterruptEnable register: bit description
Bit
Symbol
Description
31
MIE
MasterInterruptEnable by the HCD: A logic 0 is ignored by the
HC. A logic 1 enables interrupt generation by events specied in
other bits of this register.
30 to 7
-
reserved
6
RHSC
0 — ignore
1 — enable interrupt generation due to Root Hub Status Change
5
FNO
0 — ignore
1 — enable interrupt generation due to frame Number Overow
4UE
0 — ignore
1 — enable interrupt generation due to Unrecoverable Error
3RD
0 — ignore
1 — enable interrupt generation due to Resume Detect
2SF
0 — ignore
1 — enable interrupt generation due to Start of frame
1
-
reserved
0SO
0 — ignore
1 — enable interrupt generation due to Scheduling Overrun
Table 18:
HcInterruptDisable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
MIE
reserved
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
R/W
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