參數(shù)資料
型號(hào): ISP1160BD-S
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 3/88頁
文件大小: 394K
代理商: ISP1160BD-S
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
11 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Most of the ISP1160’s internal control registers are 16-bit wide. Some of the internal
control registers, however, are 32-bit wide. Figure 7 shows how the ISP1160’s 32-bit
internal control register is accessed. The complete cycle of accessing a 32-bit
register consists of a command phase followed by two data phases. In the two data
phases, the microprocessor rst reads or writes the lower 16-bit data, followed by the
upper 16-bit data.
To further describe the complete access cycles of the internal control registers, the
status of some pins of the microprocessor bus interface are shown in Figure 8.
8.4 FIFO buffer RAM access by PIO mode
Since the ISP1160’s internal memory is structured as a FIFO buffer RAM, the FIFO
buffer RAM is mapped to dedicated register elds. Therefore, accessing the internal
FIFO buffer RAM is similar to accessing the internal control registers in multiple data
phases.
Fig 6.
16-bit register access cycle.
Fig 7.
32-bit register access cycle.
Fig 8.
Accessing HC control registers.
MGT937
read/write data
(16 bits)
16-bit register access cycle
t
write command
(16 bits)
MGT938
read/write data
(lower 16 bits)
32-bit register access cycle
t
read/write data
(upper 16 bits)
write command
(16 bits)
Signals
Valid status
CS_N
0
A0
1
Valid status
0
Valid status
0
RD_N,
WR_N
RD_N = 1,
WR_N = 0
RD_N = 0 (read) or
WR_N = 0 (write)
data bus
Command code
Register data
(upper word)
Register data
(lower word)
RD_N = 0 (read) or
WR_N = 0 (write)
004aaa370
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PDF描述
ISP1160BD/01,118 UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
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