參數(shù)資料
型號: ISP1160BD-S
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 37/88頁
文件大小: 394K
代理商: ISP1160BD-S
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
42 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10.1.5
HcInterruptEnable register (R/W: 04H/84H)
Each enable bit in the HcInterruptEnable register corresponds to an associated
interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used
to control which events generate a hardware interrupt. A hardware interrupt is
requested on the host bus when three conditions occur:
A bit is set in the HcInterruptStatus register
The corresponding bit in the HcInterruptEnable register is set
Bit MasterInterruptEnable is set.
Writing a logic 1 to a bit in this register sets the corresponding bit, whereas writing a
logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the
current value of this register is returned.
Code (Hex): 04 — read
Code (Hex): 84 — write
Table 16:
HcInterruptEnable register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
MIE
reserved
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
RHSC
FNO
UE
RD
SF
reserved
SO
Reset
00000000
Access
R/W
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