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參數(shù)資料
| 型號： | ISL6112INZA-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 24/30頁 |
| 文件大?。?/td> | 938K |
| 描述： | IC PWR CNTRLR DUAL SLT 48-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用型，PCI Express? |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 3.3V，12V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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ISL6112
24
FN6456.1
August 25, 2011
Status Register Slot B (STATB) 8-Bits, Read-Only
Common Status Register (CS) 8-Bits, Read/Write
TABLE 8. STATUS REGISTER, SLOT B (STATB)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
read-only
read-only
read-only
read/write read-only read/write read-only read/write
FAULTB
MAINB
VAUXB
VAUXBF
Reserved
12VBF Reserved
3VBF
BIT(s)
FUNCTION
OPERATION
FAULTB
FAULT Pin Status - Slot B
1 = Fault pin asserted (FAULT
B pin is LOW); 0 = Fault pin
deasserted (FAULT
B pin is HIGH). See Notes 15, 16, and
17.
MAINB
MAIN Enable Status - Slot B
Represents the actual state (on/off) of the four Main
Power outputs for Slot B (+12V and +3.3V):
1 = MAIN Power ON
0 = MAIN Power OFF
VAUXB
VAUX Enable Status - Slot B
Represents the actual state (on/off) of the Auxiliary Power
output for Slot B:
1 = AUX Power ON
0 = AUX Power OFF
VAUXBF Overcurrent Fault: VAUXB supply
1 = Fault; 0 = No fault
D[3]
Reserved
Always read as zero
12VBF
Overcurrent Fault: +12V supply
1 = Fault; 0 = No fault
D[1]
Reserved
Always read as zero
3VBF
Over current Fault: 3.3V supply
1 = Fault; 0 = No fault
Power-Up Default Value:
0000 0000h = 00h
Command_Byte Value (R/W):
0000 0101
b
= 05
h
The power-up default value is 00
h
. Both slots are disabled upon power-up; i.e., all supply outputs are off. In response to an overcurrent fault condition,
writing a logical 1 back into the active (or set) bit position will clear the bit and deassert INT
. The status of the FAULT
B pin is not affected by reading the
Status Register or by clearing active status bits.
NOTES:
15. If FAULTB has been set by an overcurrent condition on one or more of the MAIN outputs, the ONB input must go LOW to reset FAULTB. If FAULTB
has been set by a VAUXB overcurrent event, the AUXENB input must go LOW to reset FAULTB. If an overcurrent has occurred on both a MAIN output
and the VAUX output of Slot B, both ONB and AUXENB of the slot must go low to reset FAULTB.
16. Neither the FAULTB bits nor the FAULT
B pins are active when the ISL6112 power paths are controlled by SMI. When using SMI power path control,
the AUXENB and ONB pins for that slot must be tied to GND.
17. If FORCE_ON
B is asserted (low), the FAULT
B pin will be unconditionally forced to its open-drain state. Note that the value in the FAULTB register bit
is not affected by FORCE_ON
B, but will instead continue to read as a high if no faults are present on Slot B, and as a low if any fault conditions exist
that would disable Slot B if FORCE_ON
B was not asserted.
TABLE 9. COMMON STATUS REGISTER (CS)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
read-write read-write read-only read-only read-write read-write read-write read-only
Reserved Reserved
GPI_B0
GPI_A0
INTMSK
UV_INT
OT_INT
Reserved
BIT(s)
FUNCTION
OPERATION
D[7] Reserved
Always read as zero
D[6] Reserved
Always read as zero
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