參數(shù)資料
型號(hào)： ISL6112INZA-T
廠商： Intersil
文件頁(yè)數(shù)： 23/30頁(yè)
文件大?。?/td> 938K
描述： IC PWR CNTRLR DUAL SLT 48-TQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 熱交換控制器
應(yīng)用： 通用型，PCI Express?
內(nèi)部開關(guān)： 無
電源電壓： 3.3V，12V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 帶卷 (TR)
ISL6112
23
FN6456.1
August 25, 2011
Control Register, Slot B (CNTRLB) 8-Bits, Read/Write
Power-Up Default Value:
 0000 0000
b
 = 00
h
Command_Byte Value (R/W):
 0000 0100
b
 = 04
h
The power-up default value is 00
h
. Both slots are disabled upon power-up; i.e., all supply outputs are off. In response to an overcurrent fault condition,
writing a Logical 1 back into the active (or set) bit position will clear the bit and deassert INT
. The status of the FAULT
A pin is not affected by reading
the Status Register or by clearing active status bits.
NOTES:
10. If FAULTA has been set by an overcurrent condition on one or more of the MAIN outputs, the ONA input must go LOW to reset FAULTA. If FAULTA has
been set by a VAUXA overcurrent event, the AUXENA input must go LOW to reset FAULTA. If an overcurrent has occurred on both a MAIN output and
the VAUX output of slot A, both ONA and AUXENA of the slot must go low to reset FAULTA.
11. Neither the FAULTA bits nor the FAULT
A pins are active when the ISL6112 power paths are controlled by SMI. When using SMI power path control,
AUXENA and ONA pins for that slot must be tied to GND.
12. If FORCE_ON
A is asserted (low), the FAULT
A pin will be unconditionally forced to its open-drain state. Note that the value in the FAULTA register bit
is not affected by FORCE_ON
A. It will instead continue to read as a high if no faults are present on Slot A, and as a low if any fault conditions exist
that would disable Slot A if FORCE_ON
A was not asserted.
TABLE 7. CONTROL REGISTER, SLOT B (CNTRLB)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]     D[0]
read-only
read-only
read-only
read-only
read-only
read/write   read/write read/write
AUXBPG
MAINBPG
Reserved
Reserved
Reserved
FORCE
_B
ENABLE
MAINB    VAUXB
BIT(s)
FUNCTION
OPERATION
BIT(s)
FUNCTION
OPERATION
AUXBPG   AUX output power-good status, Slot B
1 = Power-is-Good (VAUXB Output is above its UVLO threshold)
MAINBPG   MAIN output power-good status, Slot B
1 = Power-is-Good (MAINB Outputs are above their UVLO
thresholds)
D[5]     Reserved
Always read as zero
D[4]     Reserved
Always read as zero
D[3]     Reserved
Always read as zero
FORCE
_B
ENABLE
Allows or inhibits the operation of the FORCE_ON
B input pin
0 = FORCE_ON
B is enabled
1 = FORCE_ON
B is disabled
MAINB    MAIN enable control, Slot B
0 = OFF, 1 = ON
VAUXB    VAUX enable control, Slot B
0 = OFF, 1 = ON
Power-Up Default Value:
0000 0000
b
 = 00
h
 
Command_Byte Value (R/W):
0000 0011
b
 = 03
h
 
The power-up default value is 00
h
. Slot is disabled upon power-up; i.e., all supply outputs are off.
NOTES:
13. The state of the PWRGD
B pin is the logical AND of the values of the AUXBPG and MAINBPG bits, except when FORCE_ON
B is asserted. If
FORCE_ON
B is asserted (the pin is pulled low), and FORCE
_BENABLE is set to a logic zero, the PWRGD
B pin will be unconditionally forced to its
open-drain (Power Not Good) state.
14. The values of the MAINBPG and AUXBPG register bits are not affected by FORCE_ON
B, but will instead continue to read as high if power is Good,
and as low if the conditions, which indicate that power is good, are not met.
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