參數(shù)資料
型號(hào)： ISL6112INZA-T
廠商： Intersil
文件頁(yè)數(shù)： 21/30頁(yè)
文件大?。?/td> 938K
描述： IC PWR CNTRLR DUAL SLT 48-TQFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 熱交換控制器
應(yīng)用： 通用型，PCI Express?
內(nèi)部開(kāi)關(guān)： 無(wú)
電源電壓： 3.3V，12V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 帶卷 (TR)
ISL6112
21
FN6456.1
August 25, 2011
ISL6112 Register Set and Programmers Model
Detailed Register Descriptions
Control Register, Slot A (CNTRLA) 8-Bits, Read/Write
FIGURE 34. READ_BYTE PROTOCOL
FIGURE 35. RECEIVE_BYTE PROTOCOL
TABLE 4. ISL6112 REGISTER ADDRESSES
TARGET REGISTER
COMMAND BYTE VALUE
POWER-ON
DEFAULT
LABEL
DESCRIPTION
READ
WRITE
CNTRLA
Control Register Slot A
02h
02h
00h
CNTRLB
Control Register Slot B
03h
03h
00h
STATA
Slot A Status
04h
04h
00h
STATB
Slot B Status
05h
05h
00h
CS
Common Status Register
06h
06h
xxxx 0000b
Reserved
Reserved/Do Not Use
07h - FFh
07h - FFh
Undefined
TABLE 5. CONTROL REGISTER, SLOT A (CNTRLA)
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
read-only
read-only
read-only
read-only
read-only     read/write    read/write    read/write
AUXAPG
MAINAPG
Reserved
Reserved
Reserved     FORCE
_A
ENABLE
MAINA
VAUXA
Timing Diagrams  (Continued)
S 1 0 0 0 A2A1A0
A2A1A0
0 A 0 0 0 0 0 X X X A S 1
0
1
0 0
D4
D5
D6    D3D2D1D0
A D7
/A P
ISL6112 DEVICE ADDRESS
DATA
CLK
COMMAND BYTE TO ISL6112
ISL6112 DEVICE ADDRESS
DATA READ FROM ISL6112
START
START
R/W
 = WRITE
R/W
 = READ
ACKNOWLEDGEACKNOWLEDGE
ACKNOWLEDGE
NOT ACKNOWLEDGE
MASTER TO DEVICE TRANSFER,
i.e., DATA DRIVEN BY MASTER.
DEVICE TO MASTER TRANSFER,
i.e., DATA DRIVEN BY DEVICE.
S 1 0 0 0 A2A1A0 1 A
D4
D5
D6    D3D2D1D0
D7
/A P
ISL6112 DEVICE ADDRESS
DATA
CLK
BYTE READ FROM ISL6112
START
STOP
R/W
 = READ
ACKNOWLEDGE
NOT ACKNOWLEDGE
MASTER TO DEVICE TRANSFER,
i.e., DATA DRIVEN BY MASTER.
DEVICE TO MASTER TRANSFER,
i.e., DATA DRIVEN BY DEVICE.
BIT(s)
FUNCTION
OPERATION
AUXAPG   AUX output power-good status, Slot A
1 = Power-is-Good (VAUXA Output is above its UVLO threshold)
MAINAPG  MAIN output power-good status, Slot A
1 = Power-is-Good (MAINA Outputs are above their UVLO
thresholds)
D[5]     Reserved
Always read as zero
D[4]     Reserved
Always read as zero
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